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Showing 1 - 10 (160 total)
 
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Mohammadreza Mehrabian, Mohammad Khayatian, Ahmed Mousa, Aviral Shrivastava, Ya-Shian Li, Patricia Derler, Edward Griffor, Hugo A. Andrade, Marc Weiss, John Eidson and Dhananjay Anand. TMA: An Efficient Timestamp-Based Monitoring Approach to Test Timing Constraints of Cyber-Physical Systems. In Proceedings of the 55th Annual Design Automation Conference (DAC), 2018. [Comment]   Bibtex entry
Keywords: CPS, cyber-physical systems, Verification.  
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Hwisoo So, Moslem Didehban, Yohan Ko, Aviral Shrivastava and Kyoungwoo Lee. EXPERT: Effective and Flexible Error Protection by Redundant Multithreading. In Proceedings of the 21st International Conference on Design Automation and Test in Europe (DATE), 2018. PDF PPT [Comment]   Bibtex entry
Keywords: Fault Injection, Multithreading, Soft Error, Verification.  
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Shail Dave, Mahesh Balasubramanian and Aviral Shrivastava. URECA: A Compiler Solution to Manage Unified Register File for CGRAs. In Proceedings of the 21st International Conference on Design Automation and Test in Europe (DATE), 2018. PDF PPT [Comment]   Bibtex entry
Keywords: CGRA, Coarse-Grained Reconfigurable Arrays, Compiler Technique, Reconfigurable computing, Register File.  
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Mahesh Balasubramanian, Shail Dave, Aviral Shrivastava and Reiley Jeyapaul. LASER: A Hardware/Software Approach to Accelerate Complicated Loops on CGRAs. In Proceedings of the 21st International Conference on Design Automation and Test in Europe (DATE), 2018. PDF PPT [Comment]   Bibtex entry
Keywords: CGRA, Coarse-Grained Reconfigurable Arrays, Instruction Scheduling.  
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Shail Dave, Mahesh Balasubramanian and Aviral Shrivastava. RAMP: Resource-Aware Mapping for CGRAs. In Proceedings of the 55th Annual Design Automation Conference (DAC), 2018. [Comment]   Bibtex entry
Keywords: CGRA, Coarse-Grained Reconfigurable Arrays, Compiler Technique, Embedded System, Modulo Scheduling, Reconfigurable computing.  
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Moslem Didehban and Aviral Shrivastava. A Compiler Technique for Processor-Wide Protection From Soft Errors in Multithreaded Environments. In IEEE Transactions on Reliability, 2018. PDF [Comment]   Bibtex entry
Keywords: Compiler Technique, Fault Injection, Multi-core Processor, Multithreading, Soft Error, Verification.  
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Reiley Jeyapaul, Abhishek Risheekesan, Aviral Shrivastava and Kyoungwoo Lee. UnSync-CMP: Multicore CMP Architecture for Energy Efficient Soft Error Reliability. In Transactions on Parallel and Distributed Systems, 2014. PDF [Comment]   Bibtex entry
Keywords: Multi-core Processor, Soft Error.  
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Mohammadreza Mehrabian, Mohammad Khayatian, Aviral Shrivastava, John Eidson, Patricia Derler, Hugo A. Andrade, Ya-Shian Li-Baboud, Edward Griffor, Marc Weiss and Kevin Stanton. Timestamp Temporal Logic (TTL) for Time Testing of Cyber-Physical Systems. In ACM Transactions on Embedded Computing Systems (TECS) , Vol. 16(169) of 5s, 2017. PDF PPT [Comment]   Bibtex entry
Keywords: CPS, cyber-physical systems, Verification.   Note: Special Issue on ESWEEK 2017 - Proceedings of the International Conference on Embedded Software (EMSOFT).
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Moslem Didehban, Aviral Shrivastava and Dheeraj Lokam. NEMESIS: A Software Approach for Computing in Presence of Soft Errors. In Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2017. PDF PPT [Comment]   Bibtex entry
Keywords: Error Correction, Fault Injection, Soft Error, Verification.  
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Jongeun Lee and Aviral Shrivastava. Compiler-managed register file protection for energy-efficient soft error reduction. In ASP-DAC '09: Proceedings of the 2009 Conference on Asia and South Pacific Design Automation, Pages 618-623, 2009. PDF PPT [Comment]   Bibtex entry
Keywords: Power, Soft Error.   Note: ISBN 978-1-4244-2748-2.
Feedback: Aviral Shrivastava
Last modified: Mon November 22 2010 23:16:55
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