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Publications of Reiley Jeyapaul (past Compiler Microarchitecture Lab member)   Download bibtex file Order by:   Type | Year
<< 2017 >> TOP
1 Add to my selection
Yohan Ko, Reiley Jeyapaul, Youngbin Kim, Kyoungwoo Lee and Aviral Shrivastava. Protecting Caches from Soft Errors: A Microarchitect's Perspective. In ACM Transactions on Embedded Computing Systems (TECS), Vol. 16(4):93:1-93:28, 2017. PDF [Comment]   Bibtex entry
Keywords: Cache Vulnerability, Error Correction, Soft Error, Verification.  
<< 2016 >> TOP
2 Add to my selection
Srinivas Karthik Tanikella, Yohan Ko, Reiley Jeyapaul, Kyoungwoo Lee and Aviral Shrivastava. GemV: A Validated Toolset for the Early Exploration of System Reliability. In Proceedings of the International Conference on Application Specific Systems, Architectures and Processors (ASAP), 2016. PDF PPT [Comment]   Bibtex entry
Keywords: Embedded System, Memory Performance, Multi-core Processor, Soft Error.  
3 Add to my selection
Reiley Jeyapaul, Roberto Flores, Alfonso Avila and Aviral Shrivastava. Systematic Methodology for the Quantitative Analysis of Pipeline-Register Reliability. In IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2016. PDF [Comment]   Bibtex entry
Keywords: Cache Vulnerability, Fault Injection, Power Efficiency, Register File, Soft Error.  
<< 2015 >> TOP
4 Add to my selection
Yohan Ko, Reiley Jeyapaul, Youngbin Kim, Kyoungwoo Lee and Aviral Shrivastava. Guidelines to Design Parity Protected Write-back L1 Data Cache. In Proceedings of The 52nd Annual Design Automation Conference (DAC), 2015. PDF PPT [Comment]   Bibtex entry
Keywords: Cache, Fault Injection, Soft Error.  
5 Add to my selection
Jared Pager, Reiley Jeyapaul and Aviral Shrivastava. A Software Scheme for Multithreading on CGRAs. In ACM Transactions on Embedded Computing Systems (TECS), 2015. PDF [Comment]   Bibtex entry
Keywords: CGRA, Coarse-Grained Reconfigurable Arrays, Embedded System, Instruction Scheduling, Multithreading, Power Efficiency.  
<< 2014 >> TOP
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Reiley Jeyapaul, Abhishek Risheekesan, Aviral Shrivastava and Kyoungwoo Lee. UnSync-CMP: Multicore CMP Architecture for Energy Efficient Soft Error Reliability. In Transactions on Parallel and Distributed Systems, 2014. PDF [Comment]   Bibtex entry
Keywords: Multi-core Processor, Soft Error.  
7 Add to my selection
Aviral Shrivastava, Abhishek Risheekesan, Reiley Jeyapaul and Carole-Jean Wu. Quantitative Analysis of Control Flow Checking Mechanisms for Soft Errors. In Proceedings of the The 51st Annual Design Automation Conference (DAC), 2014. PDF PPT [Comment]   Bibtex entry
Keywords: , CFC, Soft Error, Verification.  
<< 2013 >> TOP
8 Add to my selection
Reiley Jeyapaul and Aviral Shrivastava. Enabling Energy Efficient Reliability in Embedded Systems Through Smart Cache Cleaning. In Transactions on Design Automation of Electronic Systems, Vol. 18(4):53:1-53:25, October 2013. PDF [Comment]   Bibtex entry
Keywords: Cache, Cache Vulnerability, Soft Error.  
9 Add to my selection
Kyoungwoo Lee, Aviral Shrivastava and Reiley Jeyapaul. Power-Efficient Protection from Soft Errors. In 2013 26th International Conference on VLSI Design (VLSID 2013), 2013. PDF [Comment]   Bibtex entry
Keywords: Cache, Power Efficiency, Soft Error.  
<< 2012 >> TOP
10 Add to my selection
Kyoungwoo Lee, Aviral Shrivastava and Reiley Jeyapaul. Soft Errors: The Hardware-Software Interface. In Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, Pages 577--578, ACM, New York, NY, USA, 2012. PDF PPT [Comment]   Bibtex entry
Keywords: Cache, Cache Vulnerability, Code Placement, Embedded Processor, Power, Soft Error.  
11 Add to my selection
Reiley Jeyapaul. Smart Compilers for Reliable and Power-efficient Embedded Computing. PhD thesis, Arizona State University, May 2012. PDF PPT [Comment]   Bibtex entry
Keywords: Code Placement, Compiler Technique, Power, Power Aware Computing, Soft Error.  
<< 2011 >> TOP
12 Add to my selection
Reiley Jeyapaul, Fei Hong, Aviral Shrivastava, Abhishek Risheekesan and Kyoungwoo Lee. UnSync: A Soft-Error Resilient Redundant Multicore Architecture. In Proceedings of the International Conference on Parallel Processing (ICPP), 2011. PDF PPT [Comment]   Bibtex entry
Keywords: Multi-core Processor, Soft Error.  
13 Add to my selection
Aviral Shrivastava, Jared Pager, Reiley Jeyapaul, Mahdi Hamzeh and Sarma Vrudhula. Enabling Multithreading on CGRAs. In Proceedings of the International Conference on Parallel Processing (ICPP), 2011. PDF PPT [Comment]   Bibtex entry
Keywords: CGRA, Coarse-Grained Reconfigurable Arrays.  
14 Add to my selection
Reiley Jeyapaul and Aviral Shrivastava. Smart Cache Cleaning: Energy efficient vulnerability reduction in embedded processors. In Proceedings of the 14th international conference on Compilers, architectures and synthesis for embedded systems, Pages 105--114, ACM, 2011. PDF PPT [Comment]   Bibtex entry
Keywords: Cache, Cache Vulnerability, Soft Error.  
<< 2010 >> TOP
15 Add to my selection
Reiley Jeyapaul and Aviral Shrivastava. B2P2: bounds based procedure placement for instruction TLB power reduction in embedded systems. In Proceedings of the 13th International Workshop on Software & Compilers for Embedded Systems(SCOPES), Pages 2:1-2:10, 2010. PDF PPT [Comment]   Bibtex entry
Keywords: Code Placement, Compiler Technique, Embedded Processor, Instruction TLB, Memory Management, Power.   Note: ISBN 978-1-4503-0084-1.
16 Add to my selection
Aviral Shrivastava, Jongeun Lee and Reiley Jeyapaul. Cache Vulnerability Equations for protecting data in embedded processor caches from soft errors. In SIGPLAN, Vol. 45(4):143-152, Proceedings of the ACM SIGPLAN/SIGBED 2010 conference on Languages, compilers, and tools for embedded systems , 2010. PDF PPT [Comment]   Bibtex entry
Keywords: Cache Vulnerability, Embedded Processor, Soft Error.   Note: ISSN 0362-1340.
17 Add to my selection
Reiley Jeyapaul and Aviral Shrivastava. Code Transformations for TLB Power Reduction. In International Journal of Parallel Programming, Vol. 38(3-4):254-276, Springer US, 2010. PDF [Comment]   Bibtex entry
Keywords: Compiler Technique, Instruction TLB, Power, Power Aware Computing.   Note: ISSN 0885-7458. [Annote]
<< 2009 >> TOP
18 Add to my selection
Reiley Jeyapaul, Sandeep Marathe and Aviral Shrivastava. Code Transformations for TLB Power Reduction. In VLSID '09: Proceedings of the International Conference on VLSI Design, Pages 413-418, 2009. PDF PPT [Comment]   Bibtex entry
Keywords: Power.   Note: ISBN 978-0-7695-3506-7.
<< 2008 >> TOP
19 Add to my selection
Jonghee Yoon, Aviral Shrivastava, Sanghyun Park, Minwook Ahn, Reiley Jeyapaul and Yunheung Paek. SPKM: a novel graph drawing based algorithm for application mapping onto coarse-grained reconfigurable architectures. In ASP-DAC '08: Proceedings of the conference on Asia and South Pacific design automation, Pages 776-782, 2008. PDF PPT [Comment]   Bibtex entry
Keywords: CGRA, Coarse-Grained Reconfigurable Arrays.   Note: ISBN 978-1-4244-1922-7 (Best Paper Award Candidate).
20 Add to my selection
Reiley Jeyapaul. Static Analysis to Mitigate Soft Error Failures in Processors. Master's thesis, Arizona State University, 2008. PDF PPT [Comment]   Bibtex entry
Keywords: Cache Vulnerability, Compiler Technique, Soft Error.  
<< 2007 >> TOP
21 Add to my selection
Jonghee Yoon, Aviral Shrivastava, Sanghyun Park, Minwook Ahn, Reiley Jeyapaul and Yunheung Paek. Efficient Mapping onto Coarse-Grained Reconfigurable Architectures using Graph Drawing based Algorithm. In 2007 International Conference on VLSI Design (VLSID 2007), IEEE, 2007. PDF [Comment]   Bibtex entry
Keywords: CGRA, Coarse-Grained Reconfigurable Arrays.  
Feedback: Aviral Shrivastava
Last modified: Mon November 22 2010 16:16:55
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