<< Article (Journal) >>
publications sorted by year
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Mohammadreza Mehrabian,
Mohammad Khayatian,
Aviral Shrivastava, John Eidson, Patricia Derler, Hugo A. Andrade, Ya-Shian Li-Baboud, Edward Griffor, Marc Weiss and Kevin Stanton. Timestamp Temporal Logic (TTL) for Time Testing of Cyber-Physical Systems. In ACM Transactions on Embedded Computing Systems (TECS) , Vol. 16(169) of 5s, 2017. [Comment]  Keywords: CPS, cyber-physical systems, Verification. Note: Special Issue on ESWEEK 2017 - Proceedings of the International Conference on Embedded Software (EMSOFT).
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Aviral Shrivastava, Nikil Dutt,
Jian Cai, Majid Shoushtari, Bryan Donyanavard and Hossein Tajik. Automatic Management of Software Programmable Memories in Manycore Architectures. In IET Computers & Digital Techniques, 2016. [Comment]  Keywords: Code Management, Compiler Technique, Design Automation, Embedded Processor, Memory Management, Memory Performance, Multi-core Processor, Scratchpad Memory, Stack Data.
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Aviral Shrivastava, Deepa Kannan, Sarvesh Bhardwaj and Sarma Vrudhula. Reducing Functional Unit Power Consumption and its Variation using Leakage Sensors. In IEEE TVLSI : IEEE Transactions on Very Large Scale Integration Systems, Vol. 18(6):988-997, 2010. [Comment]  Keywords: Power, Power Aware Computing.
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Kyoungwoo Lee,
Aviral Shrivastava, Ilya Issenin, Nikil Dutt and Nalini Venkatasubramanian. Partitioning Techniques for Partially Protected Caches in Resource-Constrained Embedded Systems. In ACM TODAES: ACM Transactions on Design Automation of Embedded Systems, Vol. 15(4):30:1-30:30, October 2010. [Comment]  Keywords: Cache, Soft Error.
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Jonghee Yoon,
Aviral Shrivastava, Sanghyun Park, Minwook Ahn and Yunheung Paek. A Graph Drawing Based Spatial Mapping Algorithm for Coarse-Grained Reconfigurable Architectures. In IEEE Transactions on Very Large Scale Integrated Circuits, Vol. 17(11):1565-1579, 2009. [Comment]  Keywords: CGRA, Coarse-Grained Reconfigurable Arrays. Note: ISSN 1063-8210.
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Kyoungwoo Lee,
Aviral Shrivastava, Ilya Issenin, Nikil Dutt and Nalini Venkatasubramanian. Partially Protected Caches to Reduce Failures due to Soft Errors in Multimedia Applications. In IEEE Transactions on VLSI, Vol. 17(9):1343-1348, 2009. [Comment]  Keywords: Soft Error. Note: ISSN 1063-8210.
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Kyoungwoo Lee,
Aviral Shrivastava, Nikil Dutt and Nalini Venkatasubramanian. Data Partitioning Techniques for Partially Protected Caches to Reduce Soft Error Induced Failures. In DIPES 2008 :IFIP Conference on Distributed and Parallel Embedded Systems , Distributed Embedded Systems: Design, Middleware and Resources, Vol. 271:213-225, 2008. [Comment]  Keywords: Cache, Compiler Technique, Soft Error. Note: 10.1007/978-0-387-09661-2_21.
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Sanghyun Park,
Aviral Shrivastava, Nikil Dutt, Alexandru Nicolau, Yunheung Paek and Eugene Earlie. Register File Power Reduction Using Bypass Sensitive Compiler. In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 27(6):1155-1159, June 2008. [Comment]  Keywords: Power Aware Computing, Register File. Note: ISSN 0278-0070 .
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Sanghyun Park,
Aviral Shrivastava, Eugene Earlie, Nikil Dutt, Alexandru Nicolau and Yunheung Paek. Automatic Design Space Exploration of Register Bypasses in Embedded Processors. In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 26(12):2102-2115, 2007. [Comment]  Keywords: Compiler Technique, Embedded Processor. Note: ISSN 0278-0070.
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Prabhat Mishra,
Aviral Shrivastava and Nikil Dutt. Architecture description language (ADL)-driven software toolkit generation for architectural exploration of programmable SOCs. In ACM Transactions on Design Automation of Electronic Systems, Vol. 11(3):626-658, 2006. [Comment]  Keywords: Compiler Technique, Embedded Processor. Note: ISSN 1084-4309.
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Aviral Shrivastava, Partha Biswas, Ashok Halambi, Nikil Dutt and Alexandru Nicolau. Compilation framework for code size reduction using reduced bit-width ISAs (rSAs) In ACM Transactions on Design Automation of Electronic Systems, Vol. 11(1):123-146, 2006. [Comment]  Keywords: Compiler Technique, Embedded Processor. Note: ISSN 1084-4309.
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