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<< 2018 >>

1 Moslem Didehban and Aviral Shrivastava. A Compiler Technique for Processor-Wide Protection From Soft Errors in Multithreaded Environments. In IEEE Transactions on Reliability, 2018. [Comment]   Keywords: Compiler Technique, Fault Injection, Multi-core Processor, Multithreading, Soft Error, Verification.

<< 2017 >>

2 Yohan Ko, Reiley Jeyapaul, Youngbin Kim, Kyoungwoo Lee and Aviral Shrivastava. Protecting Caches from Soft Errors: A Microarchitect's Perspective. In ACM Transactions on Embedded Computing Systems (TECS), Vol. 16(4):93:1-93:28, 2017. [Comment]   Keywords: Cache Vulnerability, Error Correction, Soft Error, Verification.   3 Yooseong Kim, David Broman and Aviral Shrivastava. WCET-Aware Function-Level Dynamic Code Management on Scratchpad Memory. In ACM Transactions on Embedded Computing Systems (TECS), Vol. 16(4):112:1-112:26, 2017. [Comment]   Keywords: Code Management, Compiler Technique, CPS, cyber-physical systems, Scratchpad Memory, WCET.   4 Mohammadreza Mehrabian, Mohammad Khayatian, Aviral Shrivastava, John Eidson, Patricia Derler, Hugo A. Andrade, Ya-Shian Li-Baboud, Edward Griffor, Marc Weiss and Kevin Stanton. Timestamp Temporal Logic (TTL) for Time Testing of Cyber-Physical Systems. In ACM Transactions on Embedded Computing Systems (TECS) , Vol. 16(169) of 5s, 2017. [Comment]   Keywords: CPS, cyber-physical systems, Verification.   Note: Special Issue on ESWEEK 2017 - Proceedings of the International Conference on Embedded Software (EMSOFT).

<< 2016 >>

5 Aviral Shrivastava, Nikil Dutt, Jian Cai, Majid Shoushtari, Bryan Donyanavard and Hossein Tajik. Automatic Management of Software Programmable Memories in Manycore Architectures. In IET Computers & Digital Techniques, 2016. [Comment]   Keywords: Code Management, Compiler Technique, Design Automation, Embedded Processor, Memory Management, Memory Performance, Multi-core Processor, Scratchpad Memory, Stack Data.   6 Reiley Jeyapaul, Roberto Flores, Alfonso Avila and Aviral Shrivastava. Systematic Methodology for the Quantitative Analysis of Pipeline-Register Reliability. In IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2016. [Comment]   Keywords: Cache Vulnerability, Fault Injection, Power Efficiency, Register File, Soft Error.

<< 2015 >>

7 Jing Lu, Ke Bai and Aviral Shrivastava. Efficient Code Assignment Techniques for Local Memory on Software Managed Multicores. In ACM Transactions on Embedded Computing Systems (TECS), 2015. [Comment]   Keywords: Code Placement, Compiler Technique, IBM Cell, Scratchpad Memory, Software-managed multicores.   8 Jared Pager, Reiley Jeyapaul and Aviral Shrivastava. A Software Scheme for Multithreading on CGRAs. In ACM Transactions on Embedded Computing Systems (TECS), 2015. [Comment]   Keywords: CGRA, Coarse-Grained Reconfigurable Arrays, Embedded System, Instruction Scheduling, Multithreading, Power Efficiency.

<< 2014 >>

9 Reiley Jeyapaul, Abhishek Risheekesan, Aviral Shrivastava and Kyoungwoo Lee. UnSync-CMP: Multicore CMP Architecture for Energy Efficient Soft Error Reliability. In Transactions on Parallel and Distributed Systems, 2014. [Comment]   Keywords: Multi-core Processor, Soft Error.

<< 2013 >>

10 Ke Bai and Aviral Shrivastava. A Software-Only Scheme for Managing Heap Data on Limited Local Memory (LLM) Multicore Processors. In ACM TECS: ACM Transactions on Embedded Computing Systems, Vol. 13(1):5:1-5:18, August 2013. [Comment]   Keywords: Cache, Embedded Processor, Heap, Scratchpad Memory, Software-managed multicores.   11 Yooseong Kim and Aviral Shrivastava. Memory Performance Estimation of CUDA Programs. In ACM Transactions on Embedded Computing Systems, Vol. 13(21):21:1-21:22, September 2013. [Comment]   Keywords: CUDA, GPU, Memory Performance, Multi-core Processor.   12 Reiley Jeyapaul and Aviral Shrivastava. Enabling Energy Efficient Reliability in Embedded Systems Through Smart Cache Cleaning. In Transactions on Design Automation of Electronic Systems, Vol. 18(4):53:1-53:25, October 2013. [Comment]   Keywords: Cache, Cache Vulnerability, Soft Error.   13 Jongeun Lee and Aviral Shrivastava. Software-Based Register File Vulnerability Reduction for Embedded Processors. In ACM Transactions on Embedded Computing Systems, Vol. 13(1):38:1-38:20, November 2013. [Comment]   Keywords: Register File, Soft Error.

<< 2012 >>

14 Fei Hong, Aviral Shrivastava and Jongeun Lee. Return Data Interleaving for Multi-channel Embedded CMP Systems. In IEEE TVLSI: IEEE Transactions on Very Large Scale Integrated circuits, Vol. 20(7):1351-1354, July 2012. [Comment]   Keywords: Multi-core Processor.   15 Jongeun Lee and Aviral Shrivastava. PICA: Processor Idle Cycle Aggregation for Energy-Efficient Embedded Systems. In ACM TECS: ACM Transactions on Embedded Computing Systems, Vol. 11(2):26:1-26:27, 2012. [Comment]   Keywords: Embedded Processor, PICA, Power Aware Computing, Stall Cycle Aggregation.

<< 2011 >>

16 Yongjoo Kim, Jongeun Lee, Aviral Shrivastava and Yunheung Paek. Memory Access Optimization in compilation for Coarse Grain Reconfigurable Architectures. In ACM TODAES: ACM Transactions on Design Automation of Electronic Systems, Vol. 11(3):42:1-42:27, 2011. [Comment]   Keywords: CGRA, Coarse-Grained Reconfigurable Arrays.   17 Yongjoo Kim, Jongeun Lee, Aviral Shrivastava and Yunheung Paek. High Throughput Data Mapping for Coarse-Grained Reconfigurable Architectures. In IEEE TCAD: IEEE Transactions on Computer Aided Design, Vol. 30(11):1599 - 1609, 2011. [Comment]   Keywords: CGRA, Coarse-Grained Reconfigurable Arrays.   18 Jongeun Lee and Aviral Shrivastava. Static Analysis of Register File Vulnerability. In IEEE TVLSI: IEEE Transactions on Very Large Scale Integrated circuits, Vol. 30(4):606-616, April 2011. [Comment]   Keywords: Soft Error.   19 Fei Hong, Aviral Shrivastava and Jongeun Lee. Return Data Interleaving for Multi-Channel Embedded CMPs Systems. In IEEE Transactions on Very Large Scale Integration (VLSI) Systems, (12769237):1351-1354, 30 June 2011. [Comment]   Keywords: DRAM, Memory Performance, Multi-core Processor.

<< 2010 >>

20 Aviral Shrivastava, Deepa Kannan, Sarvesh Bhardwaj and Sarma Vrudhula. Reducing Functional Unit Power Consumption and its Variation using Leakage Sensors. In IEEE TVLSI : IEEE Transactions on Very Large Scale Integration Systems, Vol. 18(6):988-997, 2010. [Comment]   Keywords: Power, Power Aware Computing.   21 Kyoungwoo Lee, Aviral Shrivastava, Ilya Issenin, Nikil Dutt and Nalini Venkatasubramanian. Partitioning Techniques for Partially Protected Caches in Resource-Constrained Embedded Systems. In ACM TODAES: ACM Transactions on Design Automation of Embedded Systems, Vol. 15(4):30:1-30:30, October 2010. [Comment]   Keywords: Cache, Soft Error.   22 Jongeun Lee and Aviral Shrivastava. A Compiler-Microarchitecture Hybrid Approach to Soft Error Reduction for Register Files. In IEEE TCAD: IEEE Transactions on Computer Aided Design, Vol. 29(7):1018-1027, July 2010. [Comment]   Keywords: Compiler Technique, Register File, Soft Error.   23 Reiley Jeyapaul and Aviral Shrivastava. Code Transformations for TLB Power Reduction. In International Journal of Parallel Programming, Vol. 38(3-4):254-276, Springer US, 2010. [Comment]   Keywords: Compiler Technique, Instruction TLB, Power, Power Aware Computing.   Note: ISSN 0885-7458. [Annote]

<< 2009 >>

24 Aviral Shrivastava, Arun Kannan and Jongeun Lee. A Software-only solution to use Scratch Pads for Stack Data. In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 28(11):1719-1728, 2009. [Comment]   Keywords: Software-managed multicores, Stack Data.   Note: ISSN 0278-0070. 25 Aviral Shrivastava, Ilya Issenin and Nikil Dutt. Compiler-in-the-Loop Design Space Exploration Framework for Energy Reduction in Horizontally Partitioned Cache Architectures. In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 28(3):461-466, 2009. [Comment]   Keywords: Cache, Compiler Technique, Embedded Processor, Power Aware Computing.   Note: ISSN 0278-0070. 26 Jonghee Yoon, Aviral Shrivastava, Sanghyun Park, Minwook Ahn and Yunheung Paek. A Graph Drawing Based Spatial Mapping Algorithm for Coarse-Grained Reconfigurable Architectures. In IEEE Transactions on Very Large Scale Integrated Circuits, Vol. 17(11):1565-1579, 2009. [Comment]   Keywords: CGRA, Coarse-Grained Reconfigurable Arrays.   Note: ISSN 1063-8210. 27 Kyoungwoo Lee, Aviral Shrivastava, Ilya Issenin, Nikil Dutt and Nalini Venkatasubramanian. Partially Protected Caches to Reduce Failures due to Soft Errors in Multimedia Applications. In IEEE Transactions on VLSI, Vol. 17(9):1343-1348, 2009. [Comment]   Keywords: Soft Error.   Note: ISSN 1063-8210.

<< 2008 >>

28 Kyoungwoo Lee, Aviral Shrivastava, Nikil Dutt and Nalini Venkatasubramanian. Data Partitioning Techniques for Partially Protected Caches to Reduce Soft Error Induced Failures. In DIPES 2008 :IFIP Conference on Distributed and Parallel Embedded Systems , Distributed Embedded Systems: Design, Middleware and Resources, Vol. 271:213-225, 2008. [Comment]   Keywords: Cache, Compiler Technique, Soft Error.   Note: 10.1007/978-0-387-09661-2_21. 29 Sanghyun Park, Aviral Shrivastava, Nikil Dutt, Alexandru Nicolau, Yunheung Paek and Eugene Earlie. Register File Power Reduction Using Bypass Sensitive Compiler. In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 27(6):1155-1159, June 2008. [Comment]   Keywords: Power Aware Computing, Register File.   Note: ISSN 0278-0070 .

<< 2007 >>

30 Sanghyun Park, Aviral Shrivastava, Eugene Earlie, Nikil Dutt, Alexandru Nicolau and Yunheung Paek. Automatic Design Space Exploration of Register Bypasses in Embedded Processors. In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 26(12):2102-2115, 2007. [Comment]   Keywords: Compiler Technique, Embedded Processor.   Note: ISSN 0278-0070.

<< 2006 >>

31 Prabhat Mishra, Aviral Shrivastava and Nikil Dutt. Architecture description language (ADL)-driven software toolkit generation for architectural exploration of programmable SOCs. In ACM Transactions on Design Automation of Electronic Systems, Vol. 11(3):626-658, 2006. [Comment]   Keywords: Compiler Technique, Embedded Processor.   Note: ISSN 1084-4309. 32 Aviral Shrivastava, Eugene Earlie, Nikil Dutt and Alexandru Nicolau. Retargetable pipeline hazard detection for partially bypassed processors. In IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 14:791-801, 2006. [Comment]   Keywords: Compiler Technique, Embedded Processor.   Note: ISBN 1063-8210. 33 Aviral Shrivastava, Partha Biswas, Ashok Halambi, Nikil Dutt and Alexandru Nicolau. Compilation framework for code size reduction using reduced bit-width ISAs (rSAs) In ACM Transactions on Design Automation of Electronic Systems, Vol. 11(1):123-146, 2006. [Comment]   Keywords: Compiler Technique, Embedded Processor.   Note: ISSN 1084-4309.

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