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<< MastersThesis >> publications sorted by year   Download bibtex file
<< 2017 >> TOP
1 Add to my selection
Edward Andert. Crossroads - A Time-Sensitive Autonomous Intersection Management Technique. Master's thesis, Arizona State University, 2017. URL PDF PPT [Comment]   Bibtex entry
Keywords: cyber-physical systems, Embedded Processor.  
<< 2016 >> TOP
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Srinivas Karthik Tanikella. GemV: A Validated Micro-architecture Vulnerability Estimation Tool. Master's thesis, Arizona State University, 2016. PDF PPT [Comment]   Bibtex entry
Keywords: Cache Vulnerability, Soft Error, Verification.  
3 Add to my selection
Dheeraj Lokam. InCheck - An Integrated Recovery Methodology for Fine-grained Soft-Error Detection Schemes. Master's thesis, Arizona State University, 2016. PDF PPT [Comment]   Bibtex entry
Keywords: Error Correction, Fault Injection, Soft Error.  
4 Add to my selection
Shail Dave. Scalable Register File Architecture for CGRA Accelerators. Master's thesis, Arizona State University, 2016. PDF PPT [Comment]   Bibtex entry
Keywords: CGRA, Coarse-Grained Reconfigurable Architectures, Compiler Technique, Register File.  
<< 2015 >> TOP
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Russell Dill. Optimization of Multi-Channel BCH Error Decoding for Common Cases. Master's thesis, Arizona State University, 2015. PDF PPT [Comment]   Bibtex entry
Keywords: Error Correction, Soft Error.  
<< 2014 >> TOP
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Tushar Rawat. Enabling Multithreaded Applications on Hybrid Shared Memory Many-core Architectures. Master's thesis, Arizona State University, 2014. PDF PPT [Comment]   Bibtex entry
Keywords: Compiler Technique, Embedded Processor, Scratchpad Memory.  
7 Add to my selection
Shri Hari Rajendran Radhika. Path Selection Based Branching for Coarse Grained Reconfigurable Arrays. Master's thesis, Arizona State University, 2014. PDF PPT [Comment]   Bibtex entry
Keywords: CGRA, Coarse-Grained Reconfigurable Architectures, Compiler Technique, Embedded Processor.  
8 Add to my selection
Dipal Saluja. Register File Organization for Coarse-Grained Reconfigurable Architectures: Compiler-Microarchitecture Perspective. Master's thesis, Arizona State University, 2014. PDF PPT [Comment]   Bibtex entry
Keywords: CGRA, Coarse-Grained Reconfigurable Architectures, Compiler Technique.  
9 Add to my selection
Bryce Holton. Construction of GCCFG for Inter-procedural Optimizations in Software Managed Manycore (SMM) Master's thesis, Arizona State University, 2014. PDF PPT [Comment]   Bibtex entry
Keywords: CFC, Scratchpad Memory.  
<< 2013 >> TOP
10 Add to my selection
Abhishek Risheekesan. Quantitative Evaluation of Control-flow based Soft Error Protection Mechanisms. Master's thesis, Arizona State University, March 2013. PDF PPT [Comment]   Bibtex entry
Keywords: Soft Error.  
<< 2012 >> TOP
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Di Lu. STL on Limited Local Memory (LLM) Multi-core Processors. Master's thesis, School of Computing, Informatics, and Decision Systems Engineering (CIDSE), 2012. PDF PPT [Comment]   Bibtex entry
Keywords: Embedded Processor, Heap, IBM Cell, Memory Management, Multi-core Processor, Software-managed multicores.  
<< 2011 >> TOP
12 Add to my selection
Jared Pager. Improving CGRA Utilization by Enabling Multi-threading for Power-efficient Embedded Systems. Master's thesis, School of Computing, Informatics, and Decision Systems Engineering (CIDSE), 2011. PDF PPT [Comment]   Bibtex entry
Keywords: CGRA, Coarse-Grained Reconfigurable Architectures.  
<< 2010 >> TOP
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Saleel Kudchadker. Managing Stack Data on Limited Local Memory Multi-core Processors. Master's thesis, School of Computing, Informatics, and Decision Systems Engineering (CIDSE), 2010. PDF PPT [Comment]   Bibtex entry
Keywords: Compiler Technique, Embedded Processor, IBM Cell, Multi-core Processor, Scratchpad Memory, Software-managed multicores, Stack Data.  
14 Add to my selection
Fei Hong. UnSync: A Soft-Error Resilient Redundant CMP Architecture. Master's thesis, School of Computing, Informatics, and Decision Systems Engineering (CIDSE), 2010. PDF [Comment]   Bibtex entry
Keywords: Multi-core Processor, Soft Error.  
15 Add to my selection
Seungchul Jung. Dynamic Code Mapping for Limited Local Memory Systems. Master's thesis, School of Computing, Informatics, and Decision Systems Engineering (CIDSE), 2010. PDF PPT [Comment]   Bibtex entry
Keywords: Code Management, Compiler Technique, IBM Cell, Multi-core Processor, Scratchpad Memory, Software-managed multicores.  
<< 2009 >> TOP
16 Add to my selection
Arun Kannan. A Software-Only Solution for Stack Management on Systems with Scratch Pad Memory. Master's thesis, School of Computing, Informatics, and Decision Systems Engineering (CIDSE), 2009. PDF PPT [Comment]   Bibtex entry
Keywords: Compiler Technique, Embedded Processor, Software-managed multicores, Stack Data.  
17 Add to my selection
Amit Pabalkar. A Dynamic Code Mapping Technique for Scratch Pad Memories in Embedded Systems. Master's thesis, School of Computing, Informatics, and Decision Systems Engineering (CIDSE), 2009. PDF PPT [Comment]   Bibtex entry
Keywords: Code Management, Compiler Technique, IBM Cell, Scratchpad Memory, Software-managed multicores.  
18 Add to my selection
Rooju Chokshi. Residue number system enhancements for programmable processors. Master's thesis, School of Computing, Informatics, and Decision Systems Engineering (CIDSE), 2009. PDF PPT [Comment]   Bibtex entry
Keywords: Compiler Technique, Embedded Processor.  
19 Add to my selection
Sai Krishna Mylavarapu. Improving Application Response Times of Nand Flash based Systems. Master's thesis, School of Computing, Informatics, and Decision Systems Engineering (CIDSE), 2009. PDF PPT [Comment]   Bibtex entry
Keywords: Compiler Technique, Embedded Processor.  
<< 2008 >> TOP
20 Add to my selection
Reiley Jeyapaul. Static Analysis to Mitigate Soft Error Failures in Processors. Master's thesis, Arizona State University, 2008. PDF PPT [Comment]   Bibtex entry
Keywords: Cache Vulnerability, Compiler Technique, Soft Error.  
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Last modified: Mon November 22 2010 16:16:55
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