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    Created: 2016-10-19 12:59:03     Modified: 2016-12-26 21:34:06
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Reiley Jeyapaul, Roberto Flores, Alfonso Avila and Aviral Shrivastava. Systematic Methodology for the Quantitative Analysis of Pipeline-Register Reliability. In IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2016. PDF [Comment]   Bibtex entry
Keywords: Cache Vulnerability, Fault Injection, Power Efficiency, Register File, Soft Error.  

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