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Publication no #298   Download bibtex file Type :   Html | Bib | Both
    Created: 2016-10-19 12:59:03     Modified: 2016-12-26 21:34:06
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@Article{JeyapaulVLSI2016,
      AUTHOR = {Jeyapaul, Reiley and Flores, Roberto and Avila, Alfonso and Shrivastava, Aviral},
      TITLE = {Systematic Methodology for the Quantitative Analysis of Pipeline-Register Reliability},
      YEAR = {2016},
      JOURNAL = {IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
      PDF = {http://aviral.lab.asu.edu/bibadmin/uploads/pdf/JeyapaulTVLSI2016.pdf},
      KEYWORDS = {Cache Vulnerability, Fault Injection, Power Efficiency, Register File, Soft Error}
}
Feedback: Aviral Shrivastava
Last modified: Mon November 22 2010 16:16:55
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