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    Created: 2010-11-28 16:35:04     Modified: 2016-03-24 17:26:43
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Aviral Shrivastava, Ilya Issenin and Nikil Dutt. Compilation techniques for energy reduction in horizontally partitioned cache architectures. In CASES '05: Proceedings of the 2005 international conference on Compilers, architectures and synthesis for embedded systems, Pages 90-96, 2005. PDF PPT [Comment]   Bibtex entry
Keywords: Cache, Compiler Technique, Power Aware Computing.   Note: ISBN 1-59593-149-X.

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