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    Created: 2010-11-28 16:35:04     Modified: 2016-03-24 17:26:43
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@InProceedings{ShrivastavaCASES2005,
      AUTHOR = {Shrivastava, Aviral and Issenin, Ilya and Dutt, Nikil},
      TITLE = {Compilation techniques for energy reduction in horizontally partitioned cache architectures},
      YEAR = {2005},
      BOOKTITLE = {CASES '05: Proceedings of the 2005 international conference on Compilers, architectures and synthesis for embedded systems},
      PAGES = {90-96},
      PDF = {http://aviral.lab.asu.edu/temp/publications/papers/miniCache.pdf},
      SLIDES = {http://aviral.lab.asu.edu/temp/publications/papers/miniCache.ppt},
      NOTE = {ISBN 1-59593-149-X},
      KEYWORDS = {Cache, Compiler Technique, Power Aware Computing}
}
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Last modified: Mon November 22 2010 16:16:55
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