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    Created: 2010-11-28 17:08:02     Modified: 2016-03-24 17:11:37
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@Article{ShrivastavaTCADCIL2009,
      AUTHOR = {Shrivastava, Aviral and Issenin, Ilya and Dutt, Nikil},
      TITLE = {Compiler-in-the-Loop Design Space Exploration Framework for Energy Reduction in Horizontally Partitioned Cache Architectures},
      YEAR = {2009},
      JOURNAL = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},
      VOLUME = {28},
      NUMBER = {3},
      PAGES = {461-466},
      PDF = {http://aviral.lab.asu.edu/temp/publications/papers/hpcJournal.pdf},
      NOTE = {ISSN 0278-0070},
      KEYWORDS = {Cache, Compiler Technique, Embedded Processor, Power Aware Computing}
}
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Last modified: Mon November 22 2010 16:16:55
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