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Kyoungwoo Lee, Aviral Shrivastava, Nikil Dutt and Nalini Venkatasubramanian. Data Partitioning Techniques for Partially Protected Caches to Reduce Soft Error Induced Failures. In DIPES 2008 :IFIP Conference on Distributed and Parallel Embedded Systems , Distributed Embedded Systems: Design, Middleware and Resources, Vol. 271:213-225, 2008. PDF [Comment]   Bibtex entry
Keywords: Cache, Compiler Technique, Soft Error.   Note: 10.1007/978-0-387-09661-2_21.
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Aviral Shrivastava, Ilya Issenin and Nikil Dutt. Compiler-in-the-Loop Design Space Exploration Framework for Energy Reduction in Horizontally Partitioned Cache Architectures. In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 28(3):461-466, 2009. PDF [Comment]   Bibtex entry
Keywords: Cache, Compiler Technique, Embedded Processor, Power Aware Computing.   Note: ISSN 0278-0070.
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Kyoungwoo Lee, Aviral Shrivastava, Ilya Issenin, Nikil Dutt and Nalini Venkatasubramanian. Partitioning Techniques for Partially Protected Caches in Resource-Constrained Embedded Systems. In ACM TODAES: ACM Transactions on Design Automation of Embedded Systems, Vol. 15(4):30:1-30:30, October 2010. PDF [Comment]   Bibtex entry
Keywords: Cache, Soft Error.  
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Ke Bai and Aviral Shrivastava. A Software-Only Scheme for Managing Heap Data on Limited Local Memory (LLM) Multicore Processors. In ACM TECS: ACM Transactions on Embedded Computing Systems, Vol. 13(1):5:1-5:18, August 2013. PDF [Comment]   Bibtex entry
Keywords: Cache, Embedded Processor, Heap, Scratchpad Memory, Software-managed multicores.  
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Reiley Jeyapaul and Aviral Shrivastava. Enabling Energy Efficient Reliability in Embedded Systems Through Smart Cache Cleaning. In Transactions on Design Automation of Electronic Systems, Vol. 18(4):53:1-53:25, October 2013. PDF [Comment]   Bibtex entry
Keywords: Cache, Cache Vulnerability, Soft Error.  
InProceedingsTOP
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Sanghyun Park, Aviral Shrivastava and Yunheung Paek. Hiding cache miss penalty using priority-based execution for embedded processors. In DATE '08: Proceedings of the conference on Design, automation and test in Europe, 2008. PDF PPT [Comment]   Bibtex entry
Keywords: Cache, Embedded Processor.   Note: ISBN 978-3-9810801-3-1.
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Aviral Shrivastava, Ilya Issenin and Nikil Dutt. A compiler-in-the-loop framework to explore horizontally partitioned cache architectures. In ASP-DAC '08: Proceedings of the conference on Asia and South Pacific design automation, Pages 328-333, 2008. PDF PPT [Comment]   Bibtex entry
Keywords: Cache, Compiler Technique.   Note: ISBN 978-1-4244-1922-7.
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Aviral Shrivastava, Ilya Issenin and Nikil Dutt. Compilation techniques for energy reduction in horizontally partitioned cache architectures. In CASES '05: Proceedings of the 2005 international conference on Compilers, architectures and synthesis for embedded systems, Pages 90-96, 2005. PDF PPT [Comment]   Bibtex entry
Keywords: Cache, Compiler Technique, Power Aware Computing.   Note: ISBN 1-59593-149-X.
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Aarul Jain, Aviral Shrivastava and Chaitali Chakrabarti. LA-LRU: A Latency-Aware Replacement Policy for Variation Tolerant Caches. In Proceedings of the 24th International Conference on VLSI Design, Pages 298-303, IEEE Computer Society, 2011. PDF PPT [Comment]   Bibtex entry
Keywords: Cache, PTV.  
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Ke Bai and Aviral Shrivastava. Automatic and Efficient Heap Data Management for Limited Local Memory Multicore Architectures. In Proceedings of the 2013 International Conference on Design Automation and Test in Europe (DATE), 2013. PDF PPT [Comment]   Bibtex entry
Keywords: Cache, Compiler Technique, Embedded Processor, Heap, IBM Cell, Memory Management, Memory Performance, Multi-core Processor, Scratchpad Memory, Software-managed multicores.  
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Kyoungwoo Lee, Aviral Shrivastava and Reiley Jeyapaul. Soft Errors: The Hardware-Software Interface. In Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, Pages 577--578, ACM, New York, NY, USA, 2012. PDF PPT [Comment]   Bibtex entry
Keywords: Cache, Cache Vulnerability, Code Placement, Embedded Processor, Power, Soft Error.  
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Reiley Jeyapaul and Aviral Shrivastava. Smart Cache Cleaning: Energy efficient vulnerability reduction in embedded processors. In Proceedings of the 14th international conference on Compilers, architectures and synthesis for embedded systems, Pages 105--114, ACM, 2011. PDF PPT [Comment]   Bibtex entry
Keywords: Cache, Cache Vulnerability, Soft Error.  
13 Add to my selection
Yohan Ko, Reiley Jeyapaul, Youngbin Kim, Kyoungwoo Lee and Aviral Shrivastava. Guidelines to Design Parity Protected Write-back L1 Data Cache. In Proceedings of The 52nd Annual Design Automation Conference (DAC), 2015. PDF PPT [Comment]   Bibtex entry
Keywords: Cache, Fault Injection, Soft Error.  
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Kyoungwoo Lee, Aviral Shrivastava and Reiley Jeyapaul. Power-Efficient Protection from Soft Errors. In 2013 26th International Conference on VLSI Design (VLSID 2013), 2013. PDF [Comment]   Bibtex entry
Keywords: Cache, Power Efficiency, Soft Error.  
PhdThesisTOP
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Ke Bai. Compiler and Runtime for Memory Management on Software Managed Manycore Processors. PhD thesis, Arizona State University, February 2014. PDF PPT [Comment]   Bibtex entry
Keywords: Cache, Embedded Processor, Memory Management, Memory Performance, Multi-core Processor, Scratchpad Memory, Software-managed multicores.  
TechReportTOP
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Kyoungwoo Lee, Aviral Shrivastava, Ilya Issenin, Nikil Dutt and Nalini Venkatasubramanian. Partially Protected Caches to Reduce Failures due to Soft Errors in Mission-Critical Multimedia Systems. Technical report, University of California, Irvine, 24 June 2008. PDF [Comment]   Bibtex entry
Keywords: Cache, Cache Vulnerability, Soft Error.  
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Last modified: Mon November 22 2010 16:16:55
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