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Publications related to 'Compiler Technique'   Download bibtex file Order by:   Type | Year
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1 Add to my selection
Kyoungwoo Lee, Aviral Shrivastava, Nikil Dutt and Nalini Venkatasubramanian. Data Partitioning Techniques for Partially Protected Caches to Reduce Soft Error Induced Failures. In DIPES 2008 :IFIP Conference on Distributed and Parallel Embedded Systems , Distributed Embedded Systems: Design, Middleware and Resources, Vol. 271:213-225, 2008. URL PDF [Comment]   Bibtex entry
Keywords: Cache, Compiler Technique, SER, Soft Error.   Note: 10.1007/978-0-387-09661-2_21.
2 Add to my selection
Aviral Shrivastava, Ilya Issenin and Nikil Dutt. Compiler-in-the-Loop Design Space Exploration Framework for Energy Reduction in Horizontally Partitioned Cache Architectures. In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 28(3):461-466, 2009. PDF [Comment]   Bibtex entry
Keywords: Cache, Compiler Technique, Embedded Processor, Power Aware Computing.   Note: ISSN 0278-0070.
3 Add to my selection
Sanghyun Park, Aviral Shrivastava, Eugene Earlie, Nikil Dutt, Alexandru Nicolau and Yunheung Paek. Automatic Design Space Exploration of Register Bypasses in Embedded Processors. In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 26(12):2102-2115, 2007. PDF [Comment]   Bibtex entry
Keywords: Compiler Technique, Embedded Processor.   Note: ISSN 0278-0070.
4 Add to my selection
Prabhat Mishra, Aviral Shrivastava and Nikil Dutt. Architecture description language (ADL)-driven software toolkit generation for architectural exploration of programmable SOCs. In ACM Transactions on Design Automation of Electronic Systems, Vol. 11(3):626-658, 2006. PDF [Comment]   Bibtex entry
Keywords: Compiler Technique, Embedded Processor.   Note: ISSN 1084-4309.
5 Add to my selection
Aviral Shrivastava, Eugene Earlie, Nikil Dutt and Alexandru Nicolau. Retargetable pipeline hazard detection for partially bypassed processors. In IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 14:791-801, 2006. PDF [Comment]   Bibtex entry
Keywords: Compiler Technique, Embedded Processor.   Note: ISBN 1063-8210.
6 Add to my selection
Aviral Shrivastava, Partha Biswas, Ashok Halambi, Nikil Dutt and Alexandru Nicolau. Compilation framework for code size reduction using reduced bit-width ISAs (rSAs) In ACM Transactions on Design Automation of Electronic Systems, Vol. 11(1):123-146, 2006. PDF [Comment]   Bibtex entry
Keywords: Compiler Technique, Embedded Processor.   Note: ISSN 1084-4309.
7 Add to my selection
Jongeun Lee and Aviral Shrivastava. A Compiler-Microarchitecture Hybrid Approach to Soft Error Reduction for Register Files. In IEEE TCAD: IEEE Transactions on Computer Aided Design, Vol. 29(7):1018-1027, July 2010. PDF [Comment]   Bibtex entry
Keywords: Compiler Technique, Register File, Soft Error.  
8 Add to my selection
Reiley Jeyapaul and Aviral Shrivastava. Code Transformations for TLB Power Reduction. In International Journal of Parallel Programming, Vol. 38(3-4):254-276, Springer US, 2010. URL PDF [Comment]   Bibtex entry
Keywords: Compiler Technique, Instruction TLB, Power, Power Aware Computing.   Note: ISSN 0885-7458. [Annote]
InProceedingsTOP
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Seungchul Jung, Aviral Shrivastava and Ke Bai. Dynamic code mapping for limited local memory systems. In Proceedings of the International Conference on Application-specific Systems Architectures and Processors (ASAP), Pages 13-20, July 2010. URL PDF PPT [Comment]   Bibtex entry
Keywords: Code Placement, Compiler Technique, Embedded Processor, IBM Cell, LLM, Local Memory, Memory Management, Multi-core Processor, PS3, Scratchpad Memory.   Note: ISSN 1063-6268.
10 Add to my selection
Reiley Jeyapaul and Aviral Shrivastava. B2P2: bounds based procedure placement for instruction TLB power reduction in embedded systems. In Proceedings of the 13th International Workshop on Software & Compilers for Embedded Systems(SCOPES), Pages 2:1-2:10, 2010. URL PDF PPT [Comment]   Bibtex entry
Keywords: Code Placement, Compiler Technique, Embedded Processor, Instruction TLB, Memory Management, Power.   Note: ISBN 978-1-4503-0084-1.
11 Add to my selection
Jongeun Lee and Aviral Shrivastava. A compiler optimization to reduce soft errors in register files. In LCTES '09: Proceedings of the 2009 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems, Pages 41-49, 2009. PDF PPT [Comment]   Bibtex entry
Keywords: Compiler Technique, SER, Soft Error.   Note: ISBN 978-1-60558-356-3.
12 Add to my selection
Amit Pabalkar, Aviral Shrivastava, Arun Kannan and Jongeun Lee. SDRM: Simultaneous Determination of Regions and Function-to-Region Mapping for Scratchpad Memories. In HIPC 2008 :International Conference on High Performance Computing, Pages 569-582 , 2008. PDF PPT [Comment]   Bibtex entry
Keywords: Code Placement, Compiler Technique, LLM, Scratchpad Memory.  
13 Add to my selection
Kyoungwoo Lee, Aviral Shrivastava, Minyoung Kim, Nikil Dutt and Nalini Venkatasubramanian. Mitigating the impact of hardware defects on multimedia applications: a cross-layer approach. In MM '08: Proceeding of the 16th ACM international conference on Multimedia, Pages 319-328, 2008. PDF PPT [Comment]   Bibtex entry
Keywords: Compiler Technique, SER.   Note: ISBN 978-1-60558-303-7.
14 Add to my selection
Aviral Shrivastava, Ilya Issenin and Nikil Dutt. A compiler-in-the-loop framework to explore horizontally partitioned cache architectures. In ASP-DAC '08: Proceedings of the conference on Asia and South Pacific design automation, Pages 328-333, 2008. PDF PPT [Comment]   Bibtex entry
Keywords: Cache, Compiler Technique.   Note: ISBN 978-1-4244-1922-7.
15 Add to my selection
Aviral Shrivastava, Ilya Issenin and Nikil Dutt. Compilation techniques for energy reduction in horizontally partitioned cache architectures. In CASES '05: Proceedings of the 2005 international conference on Compilers, architectures and synthesis for embedded systems, Pages 90-96, 2005. PDF PPT [Comment]   Bibtex entry
Keywords: Cache, Compiler Technique, Power Aware Computing.   Note: ISBN 1-59593-149-X.
16 Add to my selection
Aviral Shrivastava, Mohit Kumar, Sanjiv Kapoor, Shashi Kumar and M. Balakrishnan. Optimal Hardware/Software Partitioning for Concurrent Specification Using Dynamic Programming. In VLSID '00: Proceedings of the 13th International Conference on VLSI Design, Pages 110, 2000. PDF [Comment]   Bibtex entry
Keywords: Compiler Technique.   Note: ISBN 0-7695-0487-6.
17 Add to my selection
Ke Bai and Aviral Shrivastava. Heap Data Management for Limited Local Memory (LLM) Multi-core Processors. In Proceedings of the 23th international symposium on System Synthesis (CODES+ISSS), Pages 317-326 , ACM Press, New York, NY, USA , 2010. PDF PPT [Comment]   Bibtex entry
Keywords: Compiler Technique, Embedded Processor, Heap, IBM Cell, LLM, Local Memory, Memory Management, Multi-core Processor, PS3, Scratchpad Memory.   Note: ISBN .
18 Add to my selection
Jongeun Lee and Aviral Shrivastava. Static analysis to mitigate soft errors in register files. In Design, Automation Test in Europe Conference Exhibition, 2009. DATE '09., Pages 1367 -1372, April 2009. PDF PPT [Comment]   Bibtex entry
Keywords: Compiler Technique, Microprocessor Chips, Register File, SER, Soft Error, Static Estimation.   Note: ISSN 1530-1591.
19 Add to my selection
Aviral Shrivastava, Nikil Dutt, Alexandru Nicolau and Eugene Earlie. Compiler-in-the-Loop ADL-driven Early Architectural Exploration. In TECHCON 2005: Semiconductor Research Corporation, 2005. PDF PPT [Comment]   Bibtex entry
Keywords: Compiler Technique.  
20 Add to my selection
Ke Bai, Aviral Shrivastava and Saleel Kudchadker. Stack Data Management for Limited Local Memory (LLM) Multi-core Processors. In Proceedings of the International Conference on Application Specific Systems, Architectures and Processors (ASAP), Pages 231-234, 2011. PDF PPT [Comment]   Bibtex entry
Keywords: Compiler Technique, Embedded Processor, IBM Cell, LLM, Local Memory, Memory Management, PS3, Scratchpad Memory, Stack Data.  
21 Add to my selection
Ashok Halambi, Aviral Shrivastava, Nikil Dutt and Alexandru Nicolau. A customizable compiler framework for embedded systems. In In SCOPES, Springer, 2001. PDF [Comment]   Bibtex entry
Keywords: Compiler Technique, Embedded Processor.  
22 Add to my selection
Deepa Kannan, Aviral Shrivastava, Sarvesh Bhardwaj and Sarma Vrudhula. Power Reduction of Functional Units Considering Temperature and Process Variations. In VLSID'08: Proceedings of the 21st International Conference on VLSI Design, Pages 533--539, IEEE Computer Society, Washington, DC, USA , 2008. PDF PPT [Comment]   Bibtex entry
Keywords: Compiler Technique, Embedded Processor, Power Aware Computing.   Note: ISBN 0-7695-3083-4. [Annote]
23 Add to my selection
Ke Bai, Di Lu and Aviral Shrivastava. Vector class on limited local memory (LLM) multi-core processors. In Proceedings of the 14th international conference on Compilers,architectures and synthesis for embedded systems (CASES), Pages 215--224, ACM, New York, NY, USA, 2011. URL PDF PPT [Comment]   Bibtex entry
Keywords: Compiler Technique, Embedded Processor, IBM Cell, LLM, Local Memory, Memory Management, Multi-core Processor, PS3, Scratchpad Memory, Vector.   Note: ISBN 978-1-4503-0713-0.
24 Add to my selection
Ke Bai and Aviral Shrivastava. Automatic and Efficient Heap Data Management for Limited Local Memory Multicore Architectures. In Proceedings of the 2013 International Conference on Design Automation and Test in Europe (DATE), 2013. PDF [Comment]   Bibtex entry
Keywords: Cache, Compiler Technique, Embedded Processor, Heap, IBM Cell, LLM, Local Memory, Memory Management, Memory Performance, Multi-core Processor, PS3, Scratchpad Memory.  
25 Add to my selection
Jing Lu, Ke Bai and Aviral Shrivastava. SSDM: Smart Stack Data Management for Software Managed Multicores (SMMs) In Proceedings of the 50th Design Automation Conference (DAC), 2013. PDF PPT [Comment]   Bibtex entry
Keywords: Compiler Technique, Embedded Processor, IBM Cell, LLM, Local Memory, Memory Management, Memory Performance, Multi-core Processor, PS3, Scratchpad Memory, Stack Data.  
26 Add to my selection
Ke Bai, Jing Lu, Aviral Shrivastava and Bryce Holton. CMSM: An Efficient and Effective Code Management for Software Managed Multicores. In Proceedings of the international symposium on Hardware/Software Codesign and System Synthesis (CODES+ISSS), 2013. PDF PPT [Comment]   Bibtex entry
Keywords: Code Placement, Compiler Technique, Embedded Processor, IBM Cell, LLM, Local Memory, Memory Management, Memory Performance, Multi-core Processor, PS3, Scratchpad Memory.  
InCollectionTOP
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Aviral Shrivastava and Nikil Dutt. Compiler Aided Design of Embedded Computers. In The Compiler Design Handbook: Optimizations and Machine Code Generation:2nd Edition, 2007. [Comment]   Bibtex entry
Keywords: Compiler Technique, Embedded Processor.  
MastersThesisTOP
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Arun Kannan. A Software-Only Solution for Stack Management on Systems with Scratch Pad Memory. Master's thesis, School of Computing, Informatics, and Decision Systems Engineering (CIDSE), 2009. PDF PPT [Comment]   Bibtex entry
Keywords: Compiler Technique, Embedded Processor, LLM, Stack Data.  
29 Add to my selection
Amit Pabalkar. A Dynamic Code Mapping Technique for Scratch Pad Memories in Embedded Systems. Master's thesis, School of Computing, Informatics, and Decision Systems Engineering (CIDSE), 2009. PDF PPT [Comment]   Bibtex entry
Keywords: Code Placement, Compiler Technique, Embedded Processor, LLM.  
30 Add to my selection
Rooju Chokshi. Residue number system enhancements for programmable processors. Master's thesis, School of Computing, Informatics, and Decision Systems Engineering (CIDSE), 2009. PDF PPT [Comment]   Bibtex entry
Keywords: Compiler Technique, Embedded Processor.  
31 Add to my selection
S.K. Mylavarapu. Improving Application Response Times of Nand Flash based Systems. Master's thesis, School of Computing, Informatics, and Decision Systems Engineering (CIDSE), 2009. PDF PPT [Comment]   Bibtex entry
Keywords: Compiler Technique, Embedded Processor.  
32 Add to my selection
Seungchul Jung. Dynamic Code Mapping for Limited Local Memory Architectures. Master's thesis, School of Computing, Informatics, and Decision Systems Engineering (CIDSE), 2010. PDF PPT [Comment]   Bibtex entry
Keywords: Code Placement, Compiler Technique, Embedded Processor, IBM Cell, LLM, Multi-core Processor, PS3, Scratchpad Memory.  
33 Add to my selection
Saleel Kudchadker. Managing Stack Data on Limited Local Memory Multi-core Architectures. Master's thesis, School of Computing, Informatics, and Decision Systems Engineering (CIDSE), 2010. PDF PPT [Comment]   Bibtex entry
Keywords: Compiler Technique, Embedded Processor, IBM Cell, LLM, Local Memory, Multi-core Processor, PS3, Scratchpad Memory, Stack Data.  
34 Add to my selection
Reiley Jeyapaul. Static Analysis to Mitigate Soft Error Failures in Processors. Master's thesis, Arizona State University, 2008. PDF PPT [Comment]   Bibtex entry
Keywords: Cache Vulnerability, Compiler Technique, SER, Soft Error.  
PhdThesisTOP
35 Add to my selection
Aviral Shrivastava. Compiler-in-Loop Exploration of Programmable Embedded Systems. PhD thesis, Donald Bren School of Information and Computer Sciences , 2006. PDF PPT [Comment]   Bibtex entry
Keywords: Compiler Technique, Embedded Processor.  
36 Add to my selection
Reiley Jeyapaul. Smart Compilers for Reliable and Power-efficient Embedded Computing. PhD thesis, Arizona State University, May 2012. PDF PPT [Comment]   Bibtex entry
Keywords: Code Placement, Compiler Technique, Power, Power Aware Computing, Robust, SER, Soft Error.  
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Last modified: Mon November 22 2010 16:16:55
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