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Publications related to 'DRAM'   Order by:   Type | Year

Only And Or     related to: --- BAC Cache Cache Vulnerability CFC CGRA Coarse-Grained Reconfigurable Arrays Code Management Code Placement Compiler Technique CPS CUDA cyber-physical systems Design Automation Embedded Processor Embedded System Error Correction Fault Injection Flash Memory FPGA GPU Heap IBM Cell Instruction Scheduling Instruction Set Architecture Instruction TLB Memory Management Memory Performance Modulo Scheduling Multi-core Processor Multithreading NAND Flash Systems PICA Power Power Aware Computing Power Efficiency Power gating Processor Description Language PTV Reconfigurable computing Register File RISA Scratchpad Memory SMT Processor Soft Error Software Branch Hinting Software-managed multicores Stack Data Stall Cycle Aggregation Verification WCET Wireless Sensor Network

Article (Journal)

1 Fei Hong, Aviral Shrivastava and Jongeun Lee. Return Data Interleaving for Multi-Channel Embedded CMPs Systems. In IEEE Transactions on Very Large Scale Integration (VLSI) Systems, (12769237):1351-1354, 30 June 2011. [Comment]   Keywords: DRAM, Memory Performance, Multi-core Processor.

InProceedings

2 Hokeun Kim, David Broman, Edward A. Lee, Michael Zimmer, Aviral Shrivastava and Junkwang Oh. A Predictable and Command-Level Priority-Based DRAM Controller for Mixed-Criticality Systems. Real-Time and Embedded Technology and Applications Symposium (RTAS), 2015. [Comment]   Keywords: CPS, DRAM, WCET.

Feedback: Aviral Shrivastava Last modified: Mon November 22 2010 23:16:55