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Publications related to 'Instruction Scheduling'   Order by:   Type | Year

Only And Or     related to: --- BAC Cache Cache Vulnerability CFC CGRA Coarse-Grained Reconfigurable Arrays Code Management Code Placement Compiler Technique CPS CUDA cyber-physical systems Design Automation DRAM Embedded Processor Embedded System Error Correction Fault Injection Flash Memory FPGA GPU Heap IBM Cell Instruction Set Architecture Instruction TLB Memory Management Memory Performance Modulo Scheduling Multi-core Processor Multithreading NAND Flash Systems PICA Power Power Aware Computing Power Efficiency Power gating Processor Description Language PTV Reconfigurable computing Register File RISA Scratchpad Memory SMT Processor Soft Error Software Branch Hinting Software-managed multicores Stack Data Stall Cycle Aggregation Verification WCET Wireless Sensor Network

Article (Journal)

1 Jared Pager, Reiley Jeyapaul and Aviral Shrivastava. A Software Scheme for Multithreading on CGRAs. In ACM Transactions on Embedded Computing Systems (TECS), 2015. [Comment]   Keywords: CGRA, Coarse-Grained Reconfigurable Arrays, Embedded System, Instruction Scheduling, Multithreading, Power Efficiency.

InProceedings

2 Sanghyun Park, Aviral Shrivastava, Nikil Dutt, Alexandru Nicolau, Yunheung Paek and Eugene Earlie. Bypass Aware Instruction Scheduling for Register File Power Reduction. In Proceedings of the conference on Language, Compilers and Tool support for Embedded Systems, Pages 173-181, 2006. [Comment]   Keywords: BAC, Instruction Scheduling, Register File.   Note: ISBN 0362-1340.

Feedback: Aviral Shrivastava Last modified: Mon November 22 2010 16:16:55