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Publications related to 'Instruction Set Architecture'   Order by:   Type | Year

Only And Or     related to: --- BAC Cache Cache Vulnerability CFC CGRA Coarse-Grained Reconfigurable Arrays Code Management Code Placement Compiler Technique CPS CUDA cyber-physical systems Design Automation DRAM Embedded Processor Embedded System Error Correction Fault Injection Flash Memory FPGA GPU Heap IBM Cell Instruction Scheduling Instruction TLB Memory Management Memory Performance Modulo Scheduling Multi-core Processor Multithreading NAND Flash Systems PICA Power Power Aware Computing Power Efficiency Power gating Processor Description Language PTV Reconfigurable computing Register File RISA Scratchpad Memory SMT Processor Soft Error Software Branch Hinting Software-managed multicores Stack Data Stall Cycle Aggregation Verification WCET Wireless Sensor Network

InProceedings

1 Sandro Neves Soares, Ashok Halambi, Aviral Shrivastava, Flavio Rech Wagner and Nikil Dutt. Adaptive Reduced Bit-width Instruction Set Architecture (adapt-rISA) In VLSI-SOC 2009 :Proceedings of the 17th IFIP/IEEE International Conference on Very Large Scale Integreation, Pages , 2009. [Comment]   Keywords: Instruction Set Architecture, RISA.

TechReport

2 Sudeep Pasricha, Partha Biswas, Prabhat Mishra, Aviral Shrivastava, Atri Mandal, Nikil Dutt and Alexandru Nicolau. A Framework for GUI-driven Design Space Exploration of a MIPS4K-like processor. Technical report, University of California, Irvine, April 2003. [Comment]   Keywords: Embedded Processor, Instruction Set Architecture.

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