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Publications related to 'Memory Performance'   Order by:   Type | Year

Only And Or     related to: --- Autonomous Vehicles BAC Cache Cache Vulnerability CFC CGRA Coarse-Grained Reconfigurable Arrays Code Management Code Placement Compiler Technique CPS CUDA cyber-physical systems Design Automation DRAM Embedded Processor Embedded System Error Correction Fault Injection Flash Memory FPGA GPU Heap IBM Cell Instruction Scheduling Instruction Set Architecture Instruction TLB Intersection Management Memory Management Modulo Scheduling Multi-core Processor Multithreading NAND Flash Systems PICA Power Power Aware Computing Power Efficiency Power gating Processor Description Language PTV Reconfigurable computing Register File RISA Scratchpad Memory SMT Processor Soft Error Software Branch Hinting Software-managed multicores Stack Data Stall Cycle Aggregation Verification WCET Wireless Sensor Network

Article (Journal)

1 Yooseong Kim and Aviral Shrivastava. Memory Performance Estimation of CUDA Programs. In ACM Transactions on Embedded Computing Systems, Vol. 13(21):21:1-21:22, September 2013. [Comment]   Keywords: CUDA, GPU, Memory Performance, Multi-core Processor.   2 Fei Hong, Aviral Shrivastava and Jongeun Lee. Return Data Interleaving for Multi-Channel Embedded CMPs Systems. In IEEE Transactions on Very Large Scale Integration (VLSI) Systems, (12769237):1351-1354, 30 June 2011. [Comment]   Keywords: DRAM, Memory Performance, Multi-core Processor.   3 Aviral Shrivastava, Nikil Dutt, Jian Cai, Majid Shoushtari, Bryan Donyanavard and Hossein Tajik. Automatic Management of Software Programmable Memories in Manycore Architectures. In IET Computers & Digital Techniques, 2016. [Comment]   Keywords: Code Management, Compiler Technique, Design Automation, Embedded Processor, Memory Management, Memory Performance, Multi-core Processor, Scratchpad Memory, Stack Data.

InProceedings

4 Yooseong Kim and Aviral Shrivastava. CuMAPz: A tool to Analyze Memory Access Patterns in CUDA. In Proceedings of the 48th Design Automation Conference (DAC), Pages 128-133, 2011. [Comment]   Keywords: CUDA, GPU, Memory Performance, Multi-core Processor.   5 Ke Bai and Aviral Shrivastava. Automatic and Efficient Heap Data Management for Limited Local Memory Multicore Architectures. In Proceedings of the 2013 International Conference on Design Automation and Test in Europe (DATE), 2013. [Comment]   Keywords: Cache, Compiler Technique, Embedded Processor, Heap, IBM Cell, Memory Management, Memory Performance, Multi-core Processor, Scratchpad Memory, Software-managed multicores.   6 Jing Lu, Ke Bai and Aviral Shrivastava. SSDM: Smart Stack Data Management for Software Managed Multicores (SMMs) In Proceedings of the 50th Design Automation Conference (DAC), 2013. [Comment]   Keywords: Compiler Technique, Embedded Processor, IBM Cell, Memory Management, Memory Performance, Multi-core Processor, Scratchpad Memory, Software-managed multicores, Stack Data.   7 Tushar Rawat and Aviral Shrivastava. Enabling Multi-threaded Applications on Hybrid Shared Memory Manycore Architectures. In Proceedings of the 2015 International Conference on Design Automation and Test in Europe (DATE), 2015. [Comment]   Keywords: Compiler Technique, Embedded Processor, Memory Performance, Scratchpad Memory, Software-managed multicores.   8 Srinivas Karthik Tanikella, Yohan Ko, Reiley Jeyapaul, Kyoungwoo Lee and Aviral Shrivastava. GemV: A Validated Toolset for the Early Exploration of System Reliability. In Proceedings of the International Conference on Application Specific Systems, Architectures and Processors (ASAP), 2016. [Comment]   Keywords: Embedded System, Memory Performance, Multi-core Processor, Soft Error.

PhdThesis

9 Ke Bai. Compiler and Runtime for Memory Management on Software Managed Manycore Processors. PhD thesis, Arizona State University, February 2014. [Comment]   Keywords: Cache, Embedded Processor, Memory Management, Memory Performance, Multi-core Processor, Scratchpad Memory, Software-managed multicores.

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