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Publications related to 'NAND Flash Systems'   Order by:   Type | Year

Only And Or     related to: --- BAC Cache Cache Vulnerability CFC CGRA Coarse-Grained Reconfigurable Arrays Code Management Code Placement Compiler Technique CPS CUDA cyber-physical systems Design Automation DRAM Embedded Processor Embedded System Error Correction Fault Injection Flash Memory FPGA GPU Heap IBM Cell Instruction Scheduling Instruction Set Architecture Instruction TLB Memory Management Memory Performance Modulo Scheduling Multi-core Processor Multithreading PICA Power Power Aware Computing Power Efficiency Power gating Processor Description Language PTV Reconfigurable computing Register File RISA Scratchpad Memory SMT Processor Soft Error Software Branch Hinting Software-managed multicores Stack Data Stall Cycle Aggregation Verification WCET Wireless Sensor Network

InProceedings

1 Russell Dill, Aviral Shrivastava and Hyunok Oh. Optimization of Multi-Channel BCH Error Decoding for Common Cases. In In Proceedings of the 2014 international conference on Compilers, architecture, and synthesis for embedded systems (CASES), 2015. [Comment]   Keywords: Error Correction, NAND Flash Systems.

Feedback: Aviral Shrivastava Last modified: Mon November 22 2010 16:16:55