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Publications related to 'Reconfigurable computing'   Order by:   Type | Year

Only And Or     related to: --- Autonomous Vehicles BAC Cache Cache Vulnerability CFC CGRA Coarse-Grained Reconfigurable Arrays Code Management Code Placement Compiler Technique CPS CUDA cyber-physical systems Design Automation DRAM Embedded Processor Embedded System Error Correction Fault Injection Flash Memory FPGA GPU Heap IBM Cell Instruction Scheduling Instruction Set Architecture Instruction TLB Intersection Management Memory Management Memory Performance Modulo Scheduling Multi-core Processor Multithreading NAND Flash Systems PICA Power Power Aware Computing Power Efficiency Power gating Processor Description Language PTV Register File RISA Scratchpad Memory SMT Processor Soft Error Software Branch Hinting Software-managed multicores Stack Data Stall Cycle Aggregation Verification WCET Wireless Sensor Network

InProceedings

1 Hugo A. Andrade, Patricia Derler, John Eidson, Ya-Shian Li-Baboud, Aviral Shrivastava, Kevin Stanton and Marc Weiss. Towards a Reconfigurable Distributed Testbed to Enable Advanced Research and Development of Timing and Synchronization in Cyber-Physical Systems. In International Conference on ReConFigurable Computing and FPGAs (ReConFig), 2015. [Comment]   Keywords: CPS, cyber-physical systems, FPGA, Reconfigurable computing.   2 Shail Dave, Mahesh Balasubramanian and Aviral Shrivastava. URECA: A Compiler Solution to Manage Unified Register File for CGRAs. In Proceedings of the 21st International Conference on Design Automation and Test in Europe (DATE), 2018. [Comment]   Keywords: CGRA, Coarse-Grained Reconfigurable Arrays, Compiler Technique, Reconfigurable computing, Register File.   3 Shail Dave, Mahesh Balasubramanian and Aviral Shrivastava. RAMP: Resource-Aware Mapping for CGRAs. In Proceedings of the 55th Annual Design Automation Conference (DAC), 2018. [Comment]   Keywords: CGRA, Coarse-Grained Reconfigurable Arrays, Compiler Technique, Embedded System, Modulo Scheduling, Reconfigurable computing.

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