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Publications related to 'Register File'   Download bibtex file Order by:   Type | Year
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Sanghyun Park, Aviral Shrivastava, Nikil Dutt, Alexandru Nicolau, Yunheung Paek and Eugene Earlie. Register File Power Reduction Using Bypass Sensitive Compiler. In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 27(6):1155-1159, June 2008. PDF [Comment]   Bibtex entry
Keywords: Power Aware Computing, Register File.   Note: ISSN 0278-0070 .
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Jongeun Lee and Aviral Shrivastava. A Compiler-Microarchitecture Hybrid Approach to Soft Error Reduction for Register Files. In IEEE TCAD: IEEE Transactions on Computer Aided Design, Vol. 29(7):1018-1027, July 2010. PDF [Comment]   Bibtex entry
Keywords: Compiler Technique, Register File, Soft Error.  
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Jongeun Lee and Aviral Shrivastava. Software-Based Register File Vulnerability Reduction for Embedded Processors. In ACM Transactions on Embedded Computing Systems, Vol. 13(1):38:1-38:20, November 2013. PDF [Comment]   Bibtex entry
Keywords: Register File, Soft Error.  
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Reiley Jeyapaul, Roberto Flores, Alfonso Avila and Aviral Shrivastava. Systematic Methodology for the Quantitative Analysis of Pipeline-Register Reliability. In IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2016. PDF [Comment]   Bibtex entry
Keywords: Cache Vulnerability, Fault Injection, Power Efficiency, Register File, Soft Error.  
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Sanghyun Park, Aviral Shrivastava, Nikil Dutt, Alexandru Nicolau, Yunheung Paek and Eugene Earlie. Bypass Aware Instruction Scheduling for Register File Power Reduction. In Proceedings of the conference on Language, Compilers and Tool support for Embedded Systems, Pages 173-181, 2006. PDF PPT [Comment]   Bibtex entry
Keywords: BAC, Instruction Scheduling, Register File.   Note: ISBN 0362-1340.
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Jongeun Lee and Aviral Shrivastava. Static analysis to mitigate soft errors in register files. In Design, Automation Test in Europe Conference Exhibition (DATE), 2009. PDF PPT [Comment]   Bibtex entry
Keywords: Compiler Technique, Register File, Soft Error.   Note: ISSN 1530-1591.
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Shail Dave. Scalable Register File Architecture for CGRA Accelerators. Master's thesis, Arizona State University, 2016. PDF PPT [Comment]   Bibtex entry
Keywords: CGRA, Coarse-Grained Reconfigurable Arrays, Compiler Technique, Register File.  
Feedback: Aviral Shrivastava
Last modified: Mon November 22 2010 16:16:55
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