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<< Article (Journal) >> TOP
1 Add to my selection
Aviral Shrivastava, Deepa Kannan, Sarvesh Bhardwaj and Sarma Vrudhula. Reducing Functional Unit Power Consumption and its Variation using Leakage Sensors. In IEEE TVLSI : IEEE Transactions on Very Large Scale Integration Systems, Vol. 18(6):988-997, 2010. PDF [Comment]   Bibtex entry
Keywords: Power, Power Aware Computing.  
2 Add to my selection
Fei Hong, Aviral Shrivastava and Jongeun Lee. Return Data Interleaving for Multi-channel Embedded CMP Systems. In IEEE TVLSI: IEEE Transactions on Very Large Scale Integrated circuits, Vol. 20(7):1351-1354, July 2012. PDF [Comment]   Bibtex entry
Keywords: Multi-core Processor.  
3 Add to my selection
Yongjoo Kim, Jongeun Lee, Aviral Shrivastava and Yunheung Paek. Memory Access Optimization in compilation for Coarse Grain Reconfigurable Architectures. In ACM TODAES: ACM Transactions on Design Automation of Electronic Systems, Vol. 11(3):42:1-42:27, 2011. PDF [Comment]   Bibtex entry
Keywords: CGRA, Coarse-Grained Reconfigurable Arrays.  
4 Add to my selection
Yongjoo Kim, Jongeun Lee, Aviral Shrivastava and Yunheung Paek. High Throughput Data Mapping for Coarse-Grained Reconfigurable Architectures. In IEEE TCAD: IEEE Transactions on Computer Aided Design, Vol. 30(11):1599 - 1609, 2011. PDF [Comment]   Bibtex entry
Keywords: CGRA, Coarse-Grained Reconfigurable Arrays.  
5 Add to my selection
Jongeun Lee and Aviral Shrivastava. Static Analysis of Register File Vulnerability. In IEEE TVLSI: IEEE Transactions on Very Large Scale Integrated circuits, Vol. 30(4):606-616, April 2011. PDF [Comment]   Bibtex entry
Keywords: Soft Error.  
6 Add to my selection
Aviral Shrivastava, Arun Kannan and Jongeun Lee. A Software-only solution to use Scratch Pads for Stack Data. In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 28(11):1719-1728, 2009. PDF [Comment]   Bibtex entry
Keywords: Software-managed multicores, Stack Data.   Note: ISSN 0278-0070.
7 Add to my selection
Kyoungwoo Lee, Aviral Shrivastava, Nikil Dutt and Nalini Venkatasubramanian. Data Partitioning Techniques for Partially Protected Caches to Reduce Soft Error Induced Failures. In DIPES 2008 :IFIP Conference on Distributed and Parallel Embedded Systems , Distributed Embedded Systems: Design, Middleware and Resources, Vol. 271:213-225, 2008. PDF [Comment]   Bibtex entry
Keywords: Cache, Compiler Technique, Soft Error.   Note: 10.1007/978-0-387-09661-2_21.
8 Add to my selection
Aviral Shrivastava, Ilya Issenin and Nikil Dutt. Compiler-in-the-Loop Design Space Exploration Framework for Energy Reduction in Horizontally Partitioned Cache Architectures. In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 28(3):461-466, 2009. PDF [Comment]   Bibtex entry
Keywords: Cache, Compiler Technique, Embedded Processor, Power Aware Computing.   Note: ISSN 0278-0070.
9 Add to my selection
Jongeun Lee and Aviral Shrivastava. PICA: Processor Idle Cycle Aggregation for Energy-Efficient Embedded Systems. In ACM TECS: ACM Transactions on Embedded Computing Systems, Vol. 11(2):26:1-26:27, 2012. PDF [Comment]   Bibtex entry
Keywords: Embedded Processor, PICA, Power Aware Computing, Stall Cycle Aggregation.  
10 Add to my selection
Jonghee Yoon, Aviral Shrivastava, Sanghyun Park, Minwook Ahn and Yunheung Paek. A Graph Drawing Based Spatial Mapping Algorithm for Coarse-Grained Reconfigurable Architectures. In IEEE Transactions on Very Large Scale Integrated Circuits, Vol. 17(11):1565-1579, 2009. PDF [Comment]   Bibtex entry
Keywords: CGRA, Coarse-Grained Reconfigurable Arrays.   Note: ISSN 1063-8210.
11 Add to my selection
Kyoungwoo Lee, Aviral Shrivastava, Ilya Issenin, Nikil Dutt and Nalini Venkatasubramanian. Partially Protected Caches to Reduce Failures due to Soft Errors in Multimedia Applications. In IEEE Transactions on VLSI, Vol. 17(9):1343-1348, 2009. PDF [Comment]   Bibtex entry
Keywords: Soft Error.   Note: ISSN 1063-8210.
12 Add to my selection
Sanghyun Park, Aviral Shrivastava, Nikil Dutt, Alexandru Nicolau, Yunheung Paek and Eugene Earlie. Register File Power Reduction Using Bypass Sensitive Compiler. In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 27(6):1155-1159, June 2008. PDF [Comment]   Bibtex entry
Keywords: Power Aware Computing, Register File.   Note: ISSN 0278-0070 .
13 Add to my selection
Sanghyun Park, Aviral Shrivastava, Eugene Earlie, Nikil Dutt, Alexandru Nicolau and Yunheung Paek. Automatic Design Space Exploration of Register Bypasses in Embedded Processors. In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 26(12):2102-2115, 2007. PDF [Comment]   Bibtex entry
Keywords: Compiler Technique, Embedded Processor.   Note: ISSN 0278-0070.
14 Add to my selection
Prabhat Mishra, Aviral Shrivastava and Nikil Dutt. Architecture description language (ADL)-driven software toolkit generation for architectural exploration of programmable SOCs. In ACM Transactions on Design Automation of Electronic Systems, Vol. 11(3):626-658, 2006. PDF [Comment]   Bibtex entry
Keywords: Compiler Technique, Embedded Processor.   Note: ISSN 1084-4309.
15 Add to my selection
Aviral Shrivastava, Eugene Earlie, Nikil Dutt and Alexandru Nicolau. Retargetable pipeline hazard detection for partially bypassed processors. In IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 14:791-801, 2006. PDF [Comment]   Bibtex entry
Keywords: Compiler Technique, Embedded Processor.   Note: ISBN 1063-8210.
16 Add to my selection
Aviral Shrivastava, Partha Biswas, Ashok Halambi, Nikil Dutt and Alexandru Nicolau. Compilation framework for code size reduction using reduced bit-width ISAs (rSAs) In ACM Transactions on Design Automation of Electronic Systems, Vol. 11(1):123-146, 2006. PDF [Comment]   Bibtex entry
Keywords: Compiler Technique, Embedded Processor.   Note: ISSN 1084-4309.
17 Add to my selection
Kyoungwoo Lee, Aviral Shrivastava, Ilya Issenin, Nikil Dutt and Nalini Venkatasubramanian. Partitioning Techniques for Partially Protected Caches in Resource-Constrained Embedded Systems. In ACM TODAES: ACM Transactions on Design Automation of Embedded Systems, Vol. 15(4):30:1-30:30, October 2010. PDF [Comment]   Bibtex entry
Keywords: Cache, Soft Error.  
18 Add to my selection
Jongeun Lee and Aviral Shrivastava. A Compiler-Microarchitecture Hybrid Approach to Soft Error Reduction for Register Files. In IEEE TCAD: IEEE Transactions on Computer Aided Design, Vol. 29(7):1018-1027, July 2010. PDF [Comment]   Bibtex entry
Keywords: Compiler Technique, Register File, Soft Error.  
19 Add to my selection
Ke Bai and Aviral Shrivastava. A Software-Only Scheme for Managing Heap Data on Limited Local Memory (LLM) Multicore Processors. In ACM TECS: ACM Transactions on Embedded Computing Systems, Vol. 13(1):5:1-5:18, August 2013. PDF [Comment]   Bibtex entry
Keywords: Cache, Embedded Processor, Heap, Scratchpad Memory, Software-managed multicores.  
20 Add to my selection
Yooseong Kim and Aviral Shrivastava. Memory Performance Estimation of CUDA Programs. In ACM Transactions on Embedded Computing Systems, Vol. 13(21):21:1-21:22, September 2013. PDF [Comment]   Bibtex entry
Keywords: CUDA, GPU, Memory Performance, Multi-core Processor.  
21 Add to my selection
Reiley Jeyapaul and Aviral Shrivastava. Enabling Energy Efficient Reliability in Embedded Systems Through Smart Cache Cleaning. In Transactions on Design Automation of Electronic Systems, Vol. 18(4):53:1-53:25, October 2013. PDF [Comment]   Bibtex entry
Keywords: Cache, Cache Vulnerability, Soft Error.  
22 Add to my selection
Reiley Jeyapaul, Abhishek Risheekesan, Aviral Shrivastava and Kyoungwoo Lee. UnSync-CMP: Multicore CMP Architecture for Energy Efficient Soft Error Reliability. In Transactions on Parallel and Distributed Systems, 2014. PDF [Comment]   Bibtex entry
Keywords: Multi-core Processor, Soft Error.  
23 Add to my selection
Jongeun Lee and Aviral Shrivastava. Software-Based Register File Vulnerability Reduction for Embedded Processors. In ACM Transactions on Embedded Computing Systems, Vol. 13(1):38:1-38:20, November 2013. PDF [Comment]   Bibtex entry
Keywords: Register File, Soft Error.  
24 Add to my selection
Reiley Jeyapaul and Aviral Shrivastava. Code Transformations for TLB Power Reduction. In International Journal of Parallel Programming, Vol. 38(3-4):254-276, Springer US, 2010. PDF [Comment]   Bibtex entry
Keywords: Compiler Technique, Instruction TLB, Power, Power Aware Computing.   Note: ISSN 0885-7458. [Annote]
25 Add to my selection
Jing Lu, Ke Bai and Aviral Shrivastava. Efficient Code Assignment Techniques for Local Memory on Software Managed Multicores. In ACM Transactions on Embedded Computing Systems (TECS), 2015. PDF [Comment]   Bibtex entry
Keywords: Code Placement, Compiler Technique, IBM Cell, Scratchpad Memory, Software-managed multicores.  
26 Add to my selection
Jared Pager, Reiley Jeyapaul and Aviral Shrivastava. A Software Scheme for Multithreading on CGRAs. In ACM Transactions on Embedded Computing Systems (TECS), 2015. PDF [Comment]   Bibtex entry
Keywords: CGRA, Coarse-Grained Reconfigurable Arrays, Embedded System, Instruction Scheduling, Multithreading, Power Efficiency.  
27 Add to my selection
Fei Hong, Aviral Shrivastava and Jongeun Lee. Return Data Interleaving for Multi-Channel Embedded CMPs Systems. In IEEE Transactions on Very Large Scale Integration (VLSI) Systems, (12769237):1351-1354, 30 June 2011. PDF [Comment]   Bibtex entry
Keywords: DRAM, Memory Performance, Multi-core Processor.  
28 Add to my selection
Aviral Shrivastava, Nikil Dutt, Jian Cai, Majid Shoushtari, Bryan Donyanavard and Hossein Tajik. Automatic Management of Software Programmable Memories in Manycore Architectures. In IET Computers & Digital Techniques, 2016. PDF [Comment]   Bibtex entry
Keywords: Code Management, Compiler Technique, Design Automation, Embedded Processor, Memory Management, Memory Performance, Multi-core Processor, Scratchpad Memory, Stack Data.  
29 Add to my selection
Yohan Ko, Reiley Jeyapaul, Youngbin Kim, Kyoungwoo Lee and Aviral Shrivastava. Protecting Caches from Soft Errors: A Microarchitect's Perspective. In ACM Transactions on Embedded Computing Systems (TECS), Vol. 16(4):93:1-93:28, 2017. PDF [Comment]   Bibtex entry
Keywords: Cache Vulnerability, Error Correction, Soft Error, Verification.  
30 Add to my selection
Reiley Jeyapaul, Roberto Flores, Alfonso Avila and Aviral Shrivastava. Systematic Methodology for the Quantitative Analysis of Pipeline-Register Reliability. In IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2016. PDF [Comment]   Bibtex entry
Keywords: Cache Vulnerability, Fault Injection, Power Efficiency, Register File, Soft Error.  
31 Add to my selection
Yooseong Kim, David Broman and Aviral Shrivastava. WCET-Aware Function-Level Dynamic Code Management on Scratchpad Memory. In ACM Transactions on Embedded Computing Systems (TECS), Vol. 16(4):112:1-112:26, 2017. PDF [Comment]   Bibtex entry
Keywords: Code Management, Compiler Technique, CPS, cyber-physical systems, Scratchpad Memory, WCET.  
<< InProceedings >> TOP
1 Add to my selection
Aarul Jain, Aviral Shrivastava and Chaitali Chakrabarti. LA-LRU: A Latency-Aware Replacement Policy for Variation Tolerant Caches. In Proceedings of the 24th International Conference on VLSI Design, Pages 298-303, IEEE Computer Society, 2011. PDF PPT [Comment]   Bibtex entry
Keywords: Cache, PTV.  
2 Add to my selection
Aviral Shrivastava, Jongeun Lee and Reiley Jeyapaul. Cache Vulnerability Equations for protecting data in embedded processor caches from soft errors. In SIGPLAN, Vol. 45(4):143-152, Proceedings of the ACM SIGPLAN/SIGBED 2010 conference on Languages, compilers, and tools for embedded systems , 2010. PDF PPT [Comment]   Bibtex entry
Keywords: Cache Vulnerability, Embedded Processor, Soft Error.   Note: ISSN 0362-1340.
3 Add to my selection
Seungchul Jung, Aviral Shrivastava and Ke Bai. Dynamic code mapping for limited local memory systems. In Proceedings of the International Conference on Application-specific Systems Architectures and Processors (ASAP), July 2010. PDF PPT [Comment]   Bibtex entry
Keywords: Code Management, Compiler Technique, IBM Cell, Memory Management, Multi-core Processor, Scratchpad Memory, Software-managed multicores.   Note: ISSN 1063-6268.
4 Add to my selection
Xiaochen Guo, Aviral Shrivastava, Michael Spear and Gang Tan. Languages Must Expose Memory Heterogeneity. In Proceedings of the Second International Symposium on Memory Systems, 2016. PDF [Comment]   Bibtex entry
Keywords: Code Management, Compiler Technique, Flash Memory, Memory Management, Scratchpad Memory.  
5 Add to my selection
Reiley Jeyapaul and Aviral Shrivastava. B2P2: bounds based procedure placement for instruction TLB power reduction in embedded systems. In Proceedings of the 13th International Workshop on Software & Compilers for Embedded Systems(SCOPES), Pages 2:1-2:10, 2010. PDF PPT [Comment]   Bibtex entry
Keywords: Code Placement, Compiler Technique, Embedded Processor, Instruction TLB, Memory Management, Power.   Note: ISBN 978-1-4503-0084-1.
6 Add to my selection
Yongjoo Kim, Jongeun Lee, Aviral Shrivastava, Jonghee Yoon and Yunheung Paek. Operation and data mapping for CGRAs with multi-bank memory. In Proceedings of the 2010 International Conference on Languages Compilers and Tools for Embedded Systems (LCTES), Vol. 45(4):17-26, 2010. PDF PPT [Comment]   Bibtex entry
Keywords: CGRA, Coarse-Grained Reconfigurable Arrays, Memory Management.   Note: ISSN 0362-1340.
7 Add to my selection
Piotr Patronik, Krzysztof Berezowski, Stanislaw Piestrak, Janusz Biernat and Aviral Shrivastava. Fast and Energy-Efficient Constant-Coefficient FIR Filters Using Residue Number System. In Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2011. PDF [Comment]   Bibtex entry
Keywords: Power.  
8 Add to my selection
Yongjoo Kim, Jongeun Lee, Aviral Shrivastava, Jonghee Yoon and Yunheung Paek. Memory-Aware Application Mapping on Coarse Grain Reconfigurable Arrays. In Proceedings of the 2010 International Conference on High-Performance Embedded Architectures and Compilers (HIPEAC), Vol. 45(4):17-26, 2010. PDF PPT [Comment]   Bibtex entry
Keywords: CGRA, Coarse-Grained Reconfigurable Arrays.   Note: ISSN 0362-1340.
9 Add to my selection
Rooju Chokshi, Krzysztof Berezowski, Aviral Shrivastava and Stanislaw Piestrak. Exploiting residue number system for power-efficient digital signal processing in embedded processors. In CASES '09: Proceedings of the 2009 international conference on Compilers, architecture, and synthesis for embedded systems, Pages 19-28, 2009. PDF PPT [Comment]   Bibtex entry
Keywords: Embedded Processor, Power.   Note: ISBN 978-1-60558-626-7.
10 Add to my selection
Yooseong Kim and Aviral Shrivastava. CuMAPz: A tool to Analyze Memory Access Patterns in CUDA. In Proceedings of the 48th Design Automation Conference (DAC), Pages 128-133, 2011. PDF PPT [Comment]   Bibtex entry
Keywords: CUDA, GPU, Memory Performance, Multi-core Processor.  
11 Add to my selection
Jongeun Lee and Aviral Shrivastava. A compiler optimization to reduce soft errors in register files. In LCTES '09: Proceedings of the 2009 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems, Pages 41-49, 2009. PDF PPT [Comment]   Bibtex entry
Keywords: Compiler Technique, Soft Error.   Note: ISBN 978-1-60558-356-3.
12 Add to my selection
Sandro Neves Soares, Ashok Halambi, Aviral Shrivastava, Flavio Rech Wagner and Nikil Dutt. Adaptive Reduced Bit-width Instruction Set Architecture (adapt-rISA) In VLSI-SOC 2009 :Proceedings of the 17th IFIP/IEEE International Conference on Very Large Scale Integreation, Pages , 2009. PDF PPT [Comment]   Bibtex entry
Keywords: Instruction Set Architecture, RISA.  
13 Add to my selection
Sai Krishna Mylavarapu, Siddharth Choudhuri, Aviral Shrivastava, Jongeun Lee and T. Givargis. FSAF: File system aware flash translation layer for NAND Flash Memories. In Design, Automation Test in Europe Conference Exhibition (DATE), 2009. PDF PPT [Comment]   Bibtex entry
Keywords: Flash Memory.   Note: ISSN 1530-1591 .
14 Add to my selection
Reiley Jeyapaul, Fei Hong, Aviral Shrivastava, Abhishek Risheekesan and Kyoungwoo Lee. UnSync: A Soft-Error Resilient Redundant Multicore Architecture. In Proceedings of the International Conference on Parallel Processing (ICPP), 2011. PDF PPT [Comment]   Bibtex entry
Keywords: Multi-core Processor, Soft Error.  
15 Add to my selection
Jongeun Lee and Aviral Shrivastava. Static analysis to mitigate soft errors in register files. In Design, Automation Test in Europe Conference Exhibition (DATE), 2009. PDF PPT [Comment]   Bibtex entry
Keywords: Compiler Technique, Register File, Soft Error.   Note: ISSN 1530-1591.
16 Add to my selection
Arun Kannan, Aviral Shrivastava, Amit Pabalkar and Jongeun Lee. A software solution for dynamic stack management on scratch pad memory. In ASP-DAC '09: Proceedings of the 2009 Conference on Asia and South Pacific Design Automation, Pages 612-617, 2009. PDF PPT [Comment]   Bibtex entry
Keywords: Scratchpad Memory, Software-managed multicores, Stack Data.   Note: ISBN 978-1-4244-2748-2.
17 Add to my selection
Aviral Shrivastava, Jared Pager, Reiley Jeyapaul, Mahdi Hamzeh and Sarma Vrudhula. Enabling Multithreading on CGRAs. In Proceedings of the International Conference on Parallel Processing (ICPP), 2011. PDF PPT [Comment]   Bibtex entry
Keywords: CGRA, Coarse-Grained Reconfigurable Arrays.  
18 Add to my selection
Jongeun Lee and Aviral Shrivastava. Compiler-managed register file protection for energy-efficient soft error reduction. In Proceedings of the 2009 Conference on Asia and South Pacific Design Automation, Pages 618-623, 2009. PDF PPT [Comment]   Bibtex entry
Keywords: Power, Soft Error.   Note: ISBN 978-1-4244-2748-2.
19 Add to my selection
Reiley Jeyapaul, Sandeep Marathe and Aviral Shrivastava. Code Transformations for TLB Power Reduction. In VLSID '09: Proceedings of the International Conference on VLSI Design, Pages 413-418, 2009. PDF PPT [Comment]   Bibtex entry
Keywords: Power.   Note: ISBN 978-0-7695-3506-7.
20 Add to my selection
Ke Bai, Aviral Shrivastava and Saleel Kudchadker. Stack Data Management for Limited Local Memory (LLM) Multi-core Processors. In Proceedings of the International Conference on Application Specific Systems, Architectures and Processors (ASAP), 2011. PDF PPT [Comment]   Bibtex entry
Keywords: Compiler Technique, Embedded Processor, IBM Cell, Memory Management, Scratchpad Memory, Software-managed multicores, Stack Data.  
21 Add to my selection
Jongeun Lee and Aviral Shrivastava. Static analysis of processor stall cycle aggregation. In CODES/ISSS '08: Proceedings of the international conference on Hardware/Software codesign and system synthesis, Pages 25-30, 2008. PDF PPT [Comment]   Bibtex entry
Keywords: PICA, Stall Cycle Aggregation.   Note: ISBN 978-1-60558-470-6.
22 Add to my selection
Amit Pabalkar, Aviral Shrivastava, Arun Kannan and Jongeun Lee. SDRM: Simultaneous Determination of Regions and Function-to-Region Mapping for Scratchpad Memories. In HIPC 2008 :International Conference on High Performance Computing, Pages 569-582 , 2008. PDF PPT [Comment]   Bibtex entry
Keywords: Code Management, Compiler Technique, Scratchpad Memory, Software-managed multicores.  
23 Add to my selection
Kyoungwoo Lee, Aviral Shrivastava, Minyoung Kim, Nikil Dutt and Nalini Venkatasubramanian. Mitigating the impact of hardware defects on multimedia applications: a cross-layer approach. In MM '08: Proceeding of the 16th ACM international conference on Multimedia, Pages 319-328, 2008. PDF PPT [Comment]   Bibtex entry
Keywords: Compiler Technique, Soft Error.   Note: ISBN 978-1-60558-303-7.
24 Add to my selection
Jeffrey Boyd, Hari Sundaram and Aviral Shrivastava. Power-Accuracy Tradeoffs in Human Activity Transition Detection. In Proceedings of the 2010 International Conference on Design Automation and Test in Europe (DATE), 2010. PDF PPT [Comment]   Bibtex entry
Keywords: Power, Power Aware Computing.  
25 Add to my selection
Sanghyun Park, Aviral Shrivastava and Yunheung Paek. Hiding cache miss penalty using priority-based execution for embedded processors. In DATE '08: Proceedings of the conference on Design, automation and test in Europe, 2008. PDF PPT [Comment]   Bibtex entry
Keywords: Cache, Embedded Processor.   Note: ISBN 978-3-9810801-3-1.
26 Add to my selection
Jonghee Yoon, Aviral Shrivastava, Sanghyun Park, Minwook Ahn, Reiley Jeyapaul and Yunheung Paek. SPKM: a novel graph drawing based algorithm for application mapping onto coarse-grained reconfigurable architectures. In ASP-DAC '08: Proceedings of the conference on Asia and South Pacific design automation, Pages 776-782, 2008. PDF PPT [Comment]   Bibtex entry
Keywords: CGRA, Coarse-Grained Reconfigurable Arrays.   Note: ISBN 978-1-4244-1922-7 (Best Paper Award Candidate).
27 Add to my selection
Ke Bai, Di Lu and Aviral Shrivastava. Vector class on limited local memory (LLM) multi-core processors. In Proceedings of the 14th international conference on Compilers,architectures and synthesis for embedded systems (CASES), Pages 215--224, ACM, New York, NY, USA, 2011. PDF PPT [Comment]   Bibtex entry
Keywords: Compiler Technique, Embedded Processor, IBM Cell, Memory Management, Multi-core Processor, Scratchpad Memory, Software-managed multicores.   Note: ISBN 978-1-4503-0713-0.
28 Add to my selection
Aviral Shrivastava, Ilya Issenin and Nikil Dutt. A compiler-in-the-loop framework to explore horizontally partitioned cache architectures. In ASP-DAC '08: Proceedings of the conference on Asia and South Pacific design automation, Pages 328-333, 2008. PDF PPT [Comment]   Bibtex entry
Keywords: Cache, Compiler Technique.   Note: ISBN 978-1-4244-1922-7.
29 Add to my selection
Deepa Kannan, Aseem Gupta, Aviral Shrivastava, Nikil Dutt and Fadi J. Kurdahi. PTSMT: A Tool for Cross-Level Power, Performance, and Thermal Exploration of SMT Processors. In VLSID '08: Proceedings of the 21st International Conference on VLSI Design, Pages 421-427, 2008. PDF PPT [Comment]   Bibtex entry
Keywords: PTV, SMT Processor.   Note: ISBN 0-7695-3083-4.
30 Add to my selection
Deepa Kannan, Aviral Shrivastava, Vipin Mohan, Sarvesh Bhardwaj and Sarma Vrudhula. Temperature and Process Variations aware Power Gating of Functional Units. In VLSID '08: Proceedings of the 21st International Conference on VLSI Design, Pages 515-520, 2008. PDF PPT [Comment]   Bibtex entry
Keywords: Power, Power gating, PTV.   Note: ISBN 0-7695-3083-4.
31 Add to my selection
Michael A. Baker, Aviral Shrivastava and Karam S. Chatha. Smart driver for power reduction in next generation bistable electrophoretic display technology. In CODES+ISSS '07: Proceedings of international conference on Hardware/software codesign and system synthesis, Pages 197-202, 2007. PDF PPT [Comment]   Bibtex entry
Keywords: Power.   Note: ISBN 978-1-59593-824-4.
32 Add to my selection
Jonghee Yoon, Aviral Shrivastava, Sanghyun Park, Minwook Ahn and Yunheung Paek. Power Conscious Mapping onto Coarse-Grained Reconfigurable Architectures using Graph Drawing based Algorithm. In WASP '07: Workshop on Application Specific Processors, 2007. PDF PPT [Comment]   Bibtex entry
Keywords: CGRA, Coarse-Grained Reconfigurable Arrays, Power.  
33 Add to my selection
Qiang Zhu, Aviral Shrivastava and Nikil Dutt. Interactive presentation: Functional and timing validation of partially bypassed processor pipelines. In DATE '07: Proceedings of the conference on Design, automation and test in Europe, Pages 1164-1169, 2007. PDF PPT [Comment]   Bibtex entry
Keywords: BAC.   Note: ISBN 978-3-9810801-2-4.
34 Add to my selection
Satyajayant Misra, Guoliang Xue and Aviral Shrivastava. Robust Localization in Wireless Sensor Networks through the Revocation of Malicious Anchors. In ICC '07. IEEE International Conference on Communications, Pages 3057-3062, 2007. PDF PPT [Comment]   Bibtex entry
Keywords: Wireless Sensor Network.  
35 Add to my selection
Kyoungwoo Lee, Aviral Shrivastava, Ilya Issenin, Nikil Dutt and Nalini Venkatasubramanian. Mitigating soft error failures for multimedia applications by selective data protection. In CASES '06: Proceedings of the international conference on Compilers, architecture and synthesis for embedded systems, Pages 411-420, 2006. PDF PPT [Comment]   Bibtex entry
Keywords: Soft Error.   Note: ISBN 1-59593-543-6.
36 Add to my selection
Sanghyun Park, Aviral Shrivastava, Nikil Dutt, Alexandru Nicolau, Yunheung Paek and Eugene Earlie. Bypass Aware Instruction Scheduling for Register File Power Reduction. In Proceedings of the conference on Language, Compilers and Tool support for Embedded Systems, Pages 173-181, 2006. PDF PPT [Comment]   Bibtex entry
Keywords: BAC, Instruction Scheduling, Register File.   Note: ISBN 0362-1340.
37 Add to my selection
Sanghyun Park, Eugene Earlie, Aviral Shrivastava, Alexandru Nicolau, Nikil Dutt and Yunheung Paek. Automatic Generation of Operation Tables for Fast Exploration of Bypasses in Embedded Processors. In DATE '06: Proceedings of the conference on Design, automation and test in Europe, Pages 1197-1202, 2006. PDF PPT [Comment]   Bibtex entry
Keywords: BAC, Embedded Processor.   Note: ISBN 3-9810801-0-6.
38 Add to my selection
Aviral Shrivastava, Ilya Issenin and Nikil Dutt. Compilation techniques for energy reduction in horizontally partitioned cache architectures. In CASES '05: Proceedings of the 2005 international conference on Compilers, architectures and synthesis for embedded systems, Pages 90-96, 2005. PDF PPT [Comment]   Bibtex entry
Keywords: Cache, Compiler Technique, Power Aware Computing.   Note: ISBN 1-59593-149-X.
39 Add to my selection
Aviral Shrivastava, Eugene Earlie, Nikil Dutt and Alexandru Nicolau. Aggregating processor free time for energy reduction. In CODES+ISSS '05: Proceedings of the international conference on Hardware/software codesign and system synthesis, Pages 154-159, 2005. PDF PPT [Comment]   Bibtex entry
Keywords: PICA.   Note: ISBN 1-59593-161-9.
40 Add to my selection
Aviral Shrivastava, Nikil Dutt, Alexandru Nicolau and Eugene Earlie. PBExplore: A Framework for Compiler-in-the-Loop Exploration of Partial Bypassing in Embedded Processors. In DATE '05: Proceedings of the conference on Design, Automation and Test in Europe, 2005. PDF PPT [Comment]   Bibtex entry
Keywords: BAC.  
41 Add to my selection
Ashok Halambi, Aviral Shrivastava, Nikil Dutt and Alexandru Nicolau. A customizable compiler framework for embedded systems. In In SCOPES, Springer, 2001. PDF [Comment]   Bibtex entry
Keywords: Compiler Technique, Embedded Processor.  
42 Add to my selection
Aviral Shrivastava, Eugene Earlie, Nikil Dutt and Alexandru Nicolau. Operation tables for scheduling in the presence of incomplete bypassing. In CODES+ISSS, Pages 194-199 , 2004. PDF PPT [Comment]   Bibtex entry
Keywords: BAC.  
43 Add to my selection
Aviral Shrivastava and Nikil Dutt. Energy efficient code generation exploiting reduced bit-width instruction set architectures (rISA) In ASP-DAC '04: Proceedings of the 2004 conference on Asia South Pacific design automation, Pages 475-477, 2004. PDF PPT [Comment]   Bibtex entry
Keywords: RISA.   Note: ISBN 0-7803-8175-0.
44 Add to my selection
Ashok Halambi, Aviral Shrivastava, Partha Biswas, Nikil Dutt and Alexandru Nicolau. A design space exploration framework for reduced bit-width instruction set architecture (rISA) design. In ISSS '02: Proceedings of the 15th international symposium on System Synthesis, Pages 120-125, 2002. PDF PPT [Comment]   Bibtex entry
Keywords: RISA.   Note: ISBN 1-58113-576-9.
45 Add to my selection
Ashok Halambi, Aviral Shrivastava, Partha Biswas, Nikil Dutt and Alexandru Nicolau. An Efficient Compiler Technique for Code Size Reduction Using Reduced Bit-Width ISAs. In DATE '02: Proceedings of the conference on Design, automation and test in Europe, Pages 402, 2002. PDF PPT [Comment]   Bibtex entry
Keywords: RISA.  
46 Add to my selection
Aviral Shrivastava, Mohit Kumar, Sanjiv Kapoor, Shashi Kumar and M. Balakrishnan. Optimal Hardware/Software Partitioning for Concurrent Specification Using Dynamic Programming. In VLSID '00: Proceedings of the 13th International Conference on VLSI Design, Pages 110, 2000. PDF [Comment]   Bibtex entry
Keywords: Compiler Technique.   Note: ISBN 0-7695-0487-6.
47 Add to my selection
Ke Bai and Aviral Shrivastava. Automatic and Efficient Heap Data Management for Limited Local Memory Multicore Architectures. In Proceedings of the 2013 International Conference on Design Automation and Test in Europe (DATE), 2013. PDF PPT [Comment]   Bibtex entry
Keywords: Cache, Compiler Technique, Embedded Processor, Heap, IBM Cell, Memory Management, Memory Performance, Multi-core Processor, Scratchpad Memory, Software-managed multicores.  
48 Add to my selection
Aviral Shrivastava, Nikil Dutt, Alexandru Nicolau and Eugene Earlie. Compiler-in-the-Loop ADL-driven Early Architectural Exploration. In TECHCON 2005: Semiconductor Research Corporation, 2005. PDF PPT [Comment]   Bibtex entry
Keywords: Compiler Technique.  
49 Add to my selection
Deepa Kannan, Aviral Shrivastava, Sarvesh Bhardwaj and Sarma Vrudhula. Power Reduction of Functional Units Considering Temperature and Process Variations. In VLSID'08: Proceedings of the 21st International Conference on VLSI Design, Pages 533--539, IEEE Computer Society, Washington, DC, USA , 2008. PDF PPT [Comment]   Bibtex entry
Keywords: Compiler Technique, Embedded Processor, Power Aware Computing.   Note: ISBN 0-7695-3083-4. [Annote]
50 Add to my selection
Ke Bai and Aviral Shrivastava. Heap Data Management for Limited Local Memory (LLM) Multi-core Processors. In Proceedings of the 23th international symposium on System Synthesis (CODES+ISSS), Pages 317-326 , ACM Press, New York, NY, USA , 2010. PDF PPT [Comment]   Bibtex entry
Keywords: Compiler Technique, Embedded Processor, Heap, IBM Cell, Memory Management, Multi-core Processor, Scratchpad Memory, Software-managed multicores.   Note: ISBN .
51 Add to my selection
Jing Lu, Yooseong Kim, Aviral Shrivastava and Chuan Huang. Branch Penalty Reduction on IBM Cell SPUs via Software Branch Hinting. In Proceedings of CODES+ISSS, Pages 355-364, 2011. PDF PPT [Comment]   Bibtex entry
Keywords: IBM Cell, Software Branch Hinting.  
52 Add to my selection
Mahdi Hamzeh, Aviral Shrivastava and Sarma Vrudhula. EPIMap: Using Epimorphism to Map Applications on CGRAs. In Proceedings of the 49th Design Automation Conference (DAC), 2012. PDF PPT [Comment]   Bibtex entry
Keywords: CGRA, Coarse-Grained Reconfigurable Arrays.  
53 Add to my selection
Jing Lu, Ke Bai and Aviral Shrivastava. SSDM: Smart Stack Data Management for Software Managed Multicores (SMMs) In Proceedings of the 50th Design Automation Conference (DAC), 2013. PDF PPT [Comment]   Bibtex entry
Keywords: Compiler Technique, Embedded Processor, IBM Cell, Memory Management, Memory Performance, Multi-core Processor, Scratchpad Memory, Software-managed multicores, Stack Data.  
54 Add to my selection
Ke Bai, Jing Lu, Aviral Shrivastava and Bryce Holton. CMSM: An Efficient and Effective Code Management for Software Managed Multicores. In Proceedings of the international symposium on Hardware/Software Codesign and System Synthesis (CODES+ISSS), 2013. PDF PPT [Comment]   Bibtex entry
Keywords: Code Management, Compiler Technique, IBM Cell, Memory Management, Multi-core Processor, Scratchpad Memory, Software-managed multicores.  
55 Add to my selection
Kyoungwoo Lee, Aviral Shrivastava and Reiley Jeyapaul. Soft Errors: The Hardware-Software Interface. In Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, Pages 577--578, ACM, New York, NY, USA, 2012. PDF PPT [Comment]   Bibtex entry
Keywords: Cache, Cache Vulnerability, Code Placement, Embedded Processor, Power, Soft Error.  
56 Add to my selection
Reiley Jeyapaul and Aviral Shrivastava. Smart Cache Cleaning: Energy efficient vulnerability reduction in embedded processors. In Proceedings of the 14th international conference on Compilers, architectures and synthesis for embedded systems, Pages 105--114, ACM, 2011. PDF PPT [Comment]   Bibtex entry
Keywords: Cache, Cache Vulnerability, Soft Error.  
57 Add to my selection
Mahdi Hamzeh, Aviral Shrivastava and Sarma Vrudhula. REGIMap: Register-aware Application Mapping on Coarse-grained Reconfigurable Architectures (CGRAs) In Proceedings of the 50th Annual Design Automation Conference (DAC), 2013. PDF PPT [Comment]   Bibtex entry
Keywords: CGRA, Coarse-Grained Reconfigurable Arrays.  
58 Add to my selection
Yooseong Kim, David Broman, Jian Cai and Aviral Shrivastava. WCET-Aware Dynamic Code Management on Scratchpads for Software-Managed Multicores. In Proceedings of the 20th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), 2014. PDF PPT [Comment]   Bibtex entry
Keywords: Code Management, CPS, Scratchpad Memory, Software-managed multicores, WCET.  
59 Add to my selection
Bryce Holton, Ke Bai, Aviral Shrivastava and Harini Ramaprasad. Construction of GCCFG for Inter-procedural Optimizations in Software Managed Manycore (SMM) Architectures. In Proceedings of the 2014 international conference on Compilers, architecture, and synthesis for embedded systems (CASES), 2014. PDF PPT [Comment]   Bibtex entry
Keywords: Compiler Technique, Power, Scratchpad Memory, Software-managed multicores.  
60 Add to my selection
Jian Cai and Aviral Shrivastava. Software Coherence Management on Non-Coherent Cache Multi-cores. In Proceedings of 29th International Conference on VLSI Design (VLSID), 2016. PDF PPT [Comment]   Bibtex entry
Keywords: Memory Management, Multi-core Processor, Scratchpad Memory, Software-managed multicores.   Note: (Best Student Paper Award).
61 Add to my selection
Aviral Shrivastava, Abhishek Risheekesan, Reiley Jeyapaul and Carole-Jean Wu. Quantitative Analysis of Control Flow Checking Mechanisms for Soft Errors. In Proceedings of the The 51st Annual Design Automation Conference (DAC), 2014. PDF PPT [Comment]   Bibtex entry
Keywords: , CFC, Soft Error, Verification.  
62 Add to my selection
Mahdi Hamzeh, Aviral Shrivastava and Sarma Vrudhula. Branch-Aware Loop Mapping on CGRAs. In Proceedings of the The 51st Annual Design Automation Conference on Design Automation Conference, 2014. PDF PPT [Comment]   Bibtex entry
Keywords: CGRA, Coarse-Grained Reconfigurable Arrays, Compiler Technique, Modulo Scheduling.  
63 Add to my selection
David Broman, Michael Zimmer, Yooseong Kim, Hokeun Kim, Jian Cai, Aviral Shrivastava, Stephen A Edwards and Edward A. Lee. Precision Timed Infrastructure: Design Challenges. In Proceedings of the Electronic System Level Synthesis Conference (ESLsyn 2013), 2013. PDF [Comment]   Bibtex entry
Keywords: CPS, WCET.  
64 Add to my selection
Shri Hari Rajendran Radhika, Aviral Shrivastava and Mahdi Hamzeh. Path Selection Based Acceleration of Conditionals in CGRAs. In Proceedings of the 2015 International Conference on Design Automation and Test in Europe (DATE), 2015. PDF PPT [1 comment]   Bibtex entry
Keywords: CGRA, Coarse-Grained Reconfigurable Arrays, Compiler Technique.  
65 Add to my selection
Tushar Rawat and Aviral Shrivastava. Enabling Multi-threaded Applications on Hybrid Shared Memory Manycore Architectures. In Proceedings of the 2015 International Conference on Design Automation and Test in Europe (DATE), 2015. PDF PPT [Comment]   Bibtex entry
Keywords: Compiler Technique, Embedded Processor, Memory Performance, Scratchpad Memory, Software-managed multicores.  
66 Add to my selection
Yohan Ko, Reiley Jeyapaul, Youngbin Kim, Kyoungwoo Lee and Aviral Shrivastava. Guidelines to Design Parity Protected Write-back L1 Data Cache. In Proceedings of The 52nd Annual Design Automation Conference (DAC), 2015. PDF PPT [Comment]   Bibtex entry
Keywords: Cache, Fault Injection, Soft Error.  
67 Add to my selection
Moslem Didehban, Aviral Shrivastava and Dheeraj Lokam. NEMESIS: A Software Approach for Computing in Presence of Soft Errors. In Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2017. PDF [Comment]   Bibtex entry
Keywords: Error Correction, Fault Injection, Soft Error, Verification.  
68 Add to my selection
Aviral Shrivastava, Mohammadreza Mehrabian, Mohammad Khayatian, Patricia Derler, Hugo A. Andrade, Kevin Stanton, Ya-Shian Li-Baboud, Edward Griffor, Marc Weiss and John Eidson. A Testbed to Verify the Timing Behavior of Cyber-Physical Systems. In Proceedings of The 54th Annual Design Automation Conference (DAC), 2017. PDF [Comment]   Bibtex entry
Keywords: CPS, cyber-physical systems, Verification.  
69 Add to my selection
Hokeun Kim, David Broman, Edward A. Lee, Michael Zimmer, Aviral Shrivastava and Junkwang Oh. A Predictable and Command-Level Priority-Based DRAM Controller for Mixed-Criticality Systems. Real-Time and Embedded Technology and Applications Symposium (RTAS), 2015. PDF PPT [Comment]   Bibtex entry
Keywords: CPS, DRAM, WCET.  
70 Add to my selection
Tom Vander Aa, Praveen Raghavan, Scott Mahlke, Bjorn De Sutter, Aviral Shrivastava and Frank Hannig. Compilation Techniques for CGRAs: Exploring All Parallelization Approaches. Pages 185-186, Hardware/Software Codesign and System Synthesis (CODES+ISSS), 24-29 October 2010. PDF [Comment]   Bibtex entry
71 Add to my selection
Russell Dill, Aviral Shrivastava and Hyunok Oh. Optimization of Multi-Channel BCH Error Decoding for Common Cases. In In Proceedings of the 2014 international conference on Compilers, architecture, and synthesis for embedded systems (CASES), 2015. PDF PPT [Comment]   Bibtex entry
Keywords: Error Correction, NAND Flash Systems.  
72 Add to my selection
Jian Cai, Yooseong Kim, Youngbin Kim, Aviral Shrivastava and Kyoungwoo Lee. Reducing Code Management Overhead in Software-Managed Multicores. In Proceedings of the 2017 International Conference on Design Automation and Test in Europe (DATE), 2017. PDF PPT [Comment]   Bibtex entry
Keywords: Code Management, Compiler Technique, Memory Management, Scratchpad Memory.  
73 Add to my selection
Piotr Patronik, Krzysztof Berezowski, Janusz Biernat, Stanisław J. Piestrak and Aviral Shrivastava. Design of an RNS Reverse Converter for a New Five-Moduli Special Set. Pages 67-70, Proceedings of the great lakes symposium on VLSI , 2012. PDF [Comment]   Bibtex entry
74 Add to my selection
Moslem Didehban and Aviral Shrivastava. NZDC: A Compiler technique for near Zero Silent data Corruption. In Proceedings of The 53rd Annual Design Automation Conference (DAC), 2016. PDF PPT [Comment]   Bibtex entry
Keywords: Error Correction, Fault Injection, Soft Error, Verification.  
75 Add to my selection
Hugo A. Andrade, Patricia Derler, John Eidson, Ya-Shian Li-Baboud, Aviral Shrivastava, Kevin Stanton and Marc Weiss. Towards a Reconfigurable Distributed Testbed to Enable Advanced Research and Development of Timing and Synchronization in Cyber-Physical Systems. In International Conference on ReConFigurable Computing and FPGAs (ReConFig), 2015. PDF [Comment]   Bibtex entry
Keywords: CPS, cyber-physical systems, FPGA, Reconfigurable computing.  
76 Add to my selection
Kyoungwoo Lee, Aviral Shrivastava and Reiley Jeyapaul. Power-Efficient Protection from Soft Errors. In 2013 26th International Conference on VLSI Design (VLSID 2013), 2013. PDF [Comment]   Bibtex entry
Keywords: Cache, Power Efficiency, Soft Error.  
77 Add to my selection
Aviral Shrivastava. Control Flow Checking or Not?(for Soft Errors) In 2014 Conference on Computer Animation and Social Agents, 26-28 May 2014. PDF [Comment]   Bibtex entry
Keywords: CFC.  
78 Add to my selection
Kyoungwoo Lee, Aviral Shrivastava, Minyoung Kim, Nikil Dutt and Nalini Venkatasubramanian. Mitigating the Impact of Hardware Defects on Multimedia Applications – A Cross-Layer Approach. In ACM International Conference on Multimedia, ACM, 2008. PDF [Comment]   Bibtex entry
Keywords: Soft Error.  
79 Add to my selection
Moslem Didehban, Dheeraj Lokam and Aviral Shrivastava. An Integrated Safe and Fast Recovery Scheme from Soft Errors. In Proceedings of The 54th Annual Design Automation Conference (DAC), 2017. PDF PPT [Comment]   Bibtex entry
Keywords: Error Correction, Fault Injection, Soft Error, Verification.  
80 Add to my selection
Edward Andert, Mohammad Khayatian and Aviral Shrivastava. Crossroads - A Time-Sensitive Autonomous Intersection Management Technique. In Proceedings of The 54th Annual Design Automation Conference (DAC), 2017. PDF PPT [Comment]   Bibtex entry
Keywords: cyber-physical systems, Embedded Processor.   Note: (Best Paper Award Candidate).
81 Add to my selection
Jonghee Yoon, Aviral Shrivastava, Sanghyun Park, Minwook Ahn, Reiley Jeyapaul and Yunheung Paek. Efficient Mapping onto Coarse-Grained Reconfigurable Architectures using Graph Drawing based Algorithm. In 2007 International Conference on VLSI Design (VLSID 2007), IEEE, 2007. PDF [Comment]   Bibtex entry
Keywords: CGRA, Coarse-Grained Reconfigurable Arrays.  
82 Add to my selection
Jian Cai and Aviral Shrivastava. Efficient Pointer Management of Stack Data for Software Managed Multicores. In Proceedings of the International Conference on Application Specific Systems, Architectures and Processors (ASAP), 2016. PDF PPT [Comment]   Bibtex entry
Keywords: Compiler Technique, Embedded Processor, Memory Management, Multi-core Processor, Scratchpad Memory, Stack Data.  
83 Add to my selection
Srinivas Karthik Tanikella, Yohan Ko, Reiley Jeyapaul, Kyoungwoo Lee and Aviral Shrivastava. GemV: A Validated Toolset for the Early Exploration of System Reliability. In Proceedings of the International Conference on Application Specific Systems, Architectures and Processors (ASAP), 2016. PDF PPT [Comment]   Bibtex entry
Keywords: Embedded System, Memory Performance, Multi-core Processor, Soft Error.  
84 Add to my selection
Youngbin Kim, Jian Cai, Yooseong Kim, Kyoungwoo Lee and Aviral Shrivastava. Splitting Functions in Code Management on Scratchpad Memories. In Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2016. PDF PPT [Comment]   Bibtex entry
Keywords: Code Management, Compiler Technique, Embedded System, Memory Management, Multi-core Processor.  
85 Add to my selection
Aviral Shrivastava, Patricia Derler, Ya-Shian Li, Kevin Stanton, Mohammad Khayatian, Hugo A. Andrade, Marc Weiss, John Eidson and Sundeep Chandhoke. Time in Cyber-Physical Systems. In Proceedings of the international symposium on Hardware/Software Codesign and System Synthesis (CODES+ISSS), 2016. PDF [Comment]   Bibtex entry
Keywords: CPS, cyber-physical systems.  
86 Add to my selection
Mohammadreza Mehrabian, Mohammad Khayatian, Aviral Shrivastava, John Eidson, Patricia Derler, Hugo A. Andrade, Ya-Shian Li-Baboud, Edward Griffor, Marc Weiss and Kevin Stanton. Timestamp Temporal Logic (TTL) for Time Testing of Cyber-Physical Systems. In Proceedings of the International Conference on Embedded Software (EMSOFT), 2017. PDF [Comment]   Bibtex entry
Keywords: CPS, cyber-physical systems, Verification.  
<< InCollection >> TOP
1 Add to my selection
Aviral Shrivastava and Nikil Dutt. Compiler Aided Design of Embedded Computers. In The Compiler Design Handbook: Optimizations and Machine Code Generation:2nd Edition, 2007. URL [Comment]   Bibtex entry
Keywords: Compiler Technique, Embedded Processor.  
2 Add to my selection
Prabhat Mishra and Aviral Shrivastava. ADL-Driven Methodologies for Design Automation of Programmable Architectures. In Processor Description Languages: Applications and Methodologies, 2008. URL [Comment]   Bibtex entry
Keywords: Processor Description Language.  
<< InBook >> TOP
1 Add to my selection
Prabhat Mishra and Aviral Shrivastava. ADL-driven Methodologies for Design Automation of Embedded Processors. In Processor Description Languages, Pages 13-33, Chapter 2, Elsevier Inc., 2008. PDF [Comment]   Bibtex entry
Keywords: Design Automation, Embedded Processor, Embedded System.  
2 Add to my selection
Preeti Ranjan Panda, B.V.N. Silpa, Aviral Shrivastava and Krishnaiah Gummidipudi. Basic Low Power Digital Design. In Power-efficient System Design, (978-1-4419-6387-1):11-39, Chapter 2, Springer US, 2010. PDF [Comment]   Bibtex entry
Keywords: Power, Power gating.  
3 Add to my selection
Preeti Ranjan Panda, B.V.N. Silpa, Aviral Shrivastava and Krishnaiah Gummidipudi. Power Aware Operating Systems, Compilers, and Application Software. In Power-efficient System Design, (978-1-4419-6387-1):139-181, Chapter 5, Springer US, 2010. [Comment]   Bibtex entry
Keywords: Power, Power Aware Computing.  
<< MastersThesis >> TOP
1 Add to my selection
Arun Kannan. A Software-Only Solution for Stack Management on Systems with Scratch Pad Memory. Master's thesis, School of Computing, Informatics, and Decision Systems Engineering (CIDSE), 2009. PDF PPT [Comment]   Bibtex entry
Keywords: Compiler Technique, Embedded Processor, Software-managed multicores, Stack Data.  
2 Add to my selection
Saleel Kudchadker. Managing Stack Data on Limited Local Memory Multi-core Processors. Master's thesis, School of Computing, Informatics, and Decision Systems Engineering (CIDSE), 2010. PDF PPT [Comment]   Bibtex entry
Keywords: Compiler Technique, Embedded Processor, IBM Cell, Multi-core Processor, Scratchpad Memory, Software-managed multicores, Stack Data.  
3 Add to my selection
Fei Hong. UnSync: A Soft-Error Resilient Redundant CMP Architecture. Master's thesis, School of Computing, Informatics, and Decision Systems Engineering (CIDSE), 2010. PDF [Comment]   Bibtex entry
Keywords: Multi-core Processor, Soft Error.  
4 Add to my selection
Amit Pabalkar. A Dynamic Code Mapping Technique for Scratch Pad Memories in Embedded Systems. Master's thesis, School of Computing, Informatics, and Decision Systems Engineering (CIDSE), 2009. PDF PPT [Comment]   Bibtex entry
Keywords: Code Management, Compiler Technique, IBM Cell, Scratchpad Memory, Software-managed multicores.  
5 Add to my selection
Rooju Chokshi. Residue number system enhancements for programmable processors. Master's thesis, School of Computing, Informatics, and Decision Systems Engineering (CIDSE), 2009. PDF PPT [Comment]   Bibtex entry
Keywords: Compiler Technique, Embedded Processor.  
6 Add to my selection
Sai Krishna Mylavarapu. Improving Application Response Times of Nand Flash based Systems. Master's thesis, School of Computing, Informatics, and Decision Systems Engineering (CIDSE), 2009. PDF PPT [Comment]   Bibtex entry
Keywords: Compiler Technique, Embedded Processor.  
7 Add to my selection
Seungchul Jung. Dynamic Code Mapping for Limited Local Memory Systems. Master's thesis, School of Computing, Informatics, and Decision Systems Engineering (CIDSE), 2010. PDF PPT [Comment]   Bibtex entry
Keywords: Code Management, Compiler Technique, IBM Cell, Multi-core Processor, Scratchpad Memory, Software-managed multicores.  
8 Add to my selection
Jared Pager. Improving CGRA Utilization by Enabling Multi-threading for Power-efficient Embedded Systems. Master's thesis, School of Computing, Informatics, and Decision Systems Engineering (CIDSE), 2011. PDF PPT [Comment]   Bibtex entry
Keywords: CGRA, Coarse-Grained Reconfigurable Arrays.  
9 Add to my selection
Di Lu. STL on Limited Local Memory (LLM) Multi-core Processors. Master's thesis, School of Computing, Informatics, and Decision Systems Engineering (CIDSE), 2012. PDF PPT [Comment]   Bibtex entry
Keywords: Embedded Processor, Heap, IBM Cell, Memory Management, Multi-core Processor, Software-managed multicores.  
10 Add to my selection
Abhishek Risheekesan. Quantitative Evaluation of Control-flow based Soft Error Protection Mechanisms. Master's thesis, Arizona State University, March 2013. PDF PPT [Comment]   Bibtex entry
Keywords: Soft Error.  
11 Add to my selection
Reiley Jeyapaul. Static Analysis to Mitigate Soft Error Failures in Processors. Master's thesis, Arizona State University, 2008. PDF PPT [Comment]   Bibtex entry
Keywords: Cache Vulnerability, Compiler Technique, Soft Error.  
12 Add to my selection
Tushar Rawat. Enabling Multithreaded Applications on Hybrid Shared Memory Many-core Architectures. Master's thesis, Arizona State University, 2014. PDF PPT [Comment]   Bibtex entry
Keywords: Compiler Technique, Embedded Processor, Scratchpad Memory.  
13 Add to my selection
Shri Hari Rajendran Radhika. Path Selection Based Branching for Coarse Grained Reconfigurable Arrays. Master's thesis, Arizona State University, 2014. PDF PPT [Comment]   Bibtex entry
Keywords: CGRA, Coarse-Grained Reconfigurable Arrays, Compiler Technique, Embedded Processor.  
14 Add to my selection
Dipal Saluja. Register File Organization for Coarse-Grained Reconfigurable Architectures: Compiler-Microarchitecture Perspective. Master's thesis, Arizona State University, 2014. PDF PPT [Comment]   Bibtex entry
Keywords: CGRA, Coarse-Grained Reconfigurable Arrays, Compiler Technique.  
15 Add to my selection
Bryce Holton. Construction of GCCFG for Inter-procedural Optimizations in Software Managed Manycore (SMM) Master's thesis, Arizona State University, 2014. PDF PPT [Comment]   Bibtex entry
Keywords: CFC, Scratchpad Memory.  
16 Add to my selection
Russell Dill. Optimization of Multi-Channel BCH Error Decoding for Common Cases. Master's thesis, Arizona State University, 2015. PDF PPT [Comment]   Bibtex entry
Keywords: Error Correction, Soft Error.  
17 Add to my selection
Edward Andert. Crossroads - A Time-Sensitive Autonomous Intersection Management Technique. Master's thesis, Arizona State University, 2017. URL PDF PPT [Comment]   Bibtex entry
Keywords: cyber-physical systems, Embedded Processor.  
18 Add to my selection
Srinivas Karthik Tanikella. GemV: A Validated Micro-architecture Vulnerability Estimation Tool. Master's thesis, Arizona State University, 2016. PDF PPT [Comment]   Bibtex entry
Keywords: Cache Vulnerability, Soft Error, Verification.  
19 Add to my selection
Dheeraj Lokam. InCheck - An Integrated Recovery Methodology for Fine-grained Soft-Error Detection Schemes. Master's thesis, Arizona State University, 2016. PDF PPT [Comment]   Bibtex entry
Keywords: Error Correction, Fault Injection, Soft Error.  
20 Add to my selection
Shail Dave. Scalable Register File Architecture for CGRA Accelerators. Master's thesis, Arizona State University, 2016. PDF PPT [Comment]   Bibtex entry
Keywords: CGRA, Coarse-Grained Reconfigurable Arrays, Compiler Technique, Register File.  
21 Add to my selection
Jinn-Pean Lin. Optimizing Heap Data Management on Software Managed Many-core Architectures. Master's thesis, Arizona State University, 2017. PDF PPT [Comment]   Bibtex entry
Keywords: Compiler Technique, Embedded Processor, Heap, Scratchpad Memory, Software-managed multicores.  
<< PhdThesis >> TOP
1 Add to my selection
Aviral Shrivastava. Compiler-in-Loop Exploration of Programmable Embedded Systems. PhD thesis, Donald Bren School of Information and Computer Sciences , 2006. PDF PPT [Comment]   Bibtex entry
Keywords: Compiler Technique, Embedded Processor.  
2 Add to my selection
Reiley Jeyapaul. Smart Compilers for Reliable and Power-efficient Embedded Computing. PhD thesis, Arizona State University, May 2012. PDF PPT [Comment]   Bibtex entry
Keywords: Code Placement, Compiler Technique, Power, Power Aware Computing, Soft Error.  
3 Add to my selection
Ke Bai. Compiler and Runtime for Memory Management on Software Managed Manycore Processors. PhD thesis, Arizona State University, February 2014. PDF PPT [Comment]   Bibtex entry
Keywords: Cache, Embedded Processor, Memory Management, Memory Performance, Multi-core Processor, Scratchpad Memory, Software-managed multicores.  
4 Add to my selection
Mahdi Hamzeh. Compiler and Architecture Design for Coarse-Grained Programmable Accelerators. PhD thesis, Arizona State University, 2015. PDF PPT [Comment]   Bibtex entry
Keywords: CGRA, Coarse-Grained Reconfigurable Arrays.  
5 Add to my selection
Yooseong Kim. WCET-Aware Scratchpad Memory Management for Hard Real-Time Systems. PhD thesis, Arizona State University, 2017. PDF PPT [Comment]   Bibtex entry
Keywords: Code Management, CPS, cyber-physical systems, Scratchpad Memory, WCET.   Note: Outstanding Computer Science Graduating PhD Student of the Year Award.
<< TechReport >> TOP
1 Add to my selection
Sudeep Pasricha, Partha Biswas, Prabhat Mishra, Aviral Shrivastava, Atri Mandal, Nikil Dutt and Alexandru Nicolau. A Framework for GUI-driven Design Space Exploration of a MIPS4K-like processor. Technical report, University of California, Irvine, April 2003. PDF [Comment]   Bibtex entry
Keywords: Embedded Processor, Instruction Set Architecture.  
2 Add to my selection
Kyoungwoo Lee, Aviral Shrivastava, Minyoung Kim, Nikil Dutt and Nalini Venkatasubramanian. Cross-Layer Interactions of Error Control Schemes in Mobile Multimedia Systems. Technical report, University of California, Irvine, 28 July 2008. PDF [Comment]   Bibtex entry
Keywords: Error Correction, Fault Injection.  
3 Add to my selection
Kyoungwoo Lee, Aviral Shrivastava, Ilya Issenin, Nikil Dutt and Nalini Venkatasubramanian. Partially Protected Caches to Reduce Failures due to Soft Errors in Mission-Critical Multimedia Systems. Technical report, University of California, Irvine, 24 June 2008. PDF [Comment]   Bibtex entry
Keywords: Cache, Cache Vulnerability, Soft Error.  
<< Misc >> TOP
1 Add to my selection
Ke Bai and Aviral Shrivastava. Heap data management for software managed multi-core processors. https://www.google.com/patents/US9513886, 2016. [Comment]   Bibtex entry
Keywords: Compiler Technique, Heap, IBM Cell, Memory Management, Scratchpad Memory, Software-managed multicores.   Note: Patent.
2 Add to my selection
Ke Bai, Aviral Shrivastava and Jing Lu. Stack data management for software managed multi-core processors. http://www.google.com/patents/US9015689, 2015. [Comment]   Bibtex entry
Keywords: Scratchpad Memory, Software-managed multicores, Stack Data.   Note: Patent.
<< Book >> TOP
1 Add to my selection
Preeti Ranjan Panda, Aviral Shrivastava, B.V.N. Silpa and Krishnaiah Gummidipudi. Power-Efficient System Design. Springer, 1st edition edition, 2010. URL [Comment]   Bibtex entry
Keywords: Power.  
Feedback: Aviral Shrivastava
Last modified: Mon November 22 2010 16:16:55
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