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Publications of Year << 2011 >>   Download bibtex file
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Yongjoo Kim, Jongeun Lee, Aviral Shrivastava and Yunheung Paek. Memory Access Optimization in compilation for Coarse Grain Reconfigurable Architectures. In ACM TODAES: ACM Transactions on Design Automation of Electronic Systems, Vol. 11(3):42:1-42:27, 2011. PDF [Comment]   Bibtex entry
Keywords: CGRA, Coarse-Grained Reconfigurable Arrays.  
2 Add to my selection
Yongjoo Kim, Jongeun Lee, Aviral Shrivastava and Yunheung Paek. High Throughput Data Mapping for Coarse-Grained Reconfigurable Architectures. In IEEE TCAD: IEEE Transactions on Computer Aided Design, Vol. 30(11):1599 - 1609, 2011. PDF [Comment]   Bibtex entry
Keywords: CGRA, Coarse-Grained Reconfigurable Arrays.  
3 Add to my selection
Jongeun Lee and Aviral Shrivastava. Static Analysis of Register File Vulnerability. In IEEE TVLSI: IEEE Transactions on Very Large Scale Integrated circuits, Vol. 30(4):606-616, April 2011. PDF [Comment]   Bibtex entry
Keywords: Soft Error.  
4 Add to my selection
Fei Hong, Aviral Shrivastava and Jongeun Lee. Return Data Interleaving for Multi-Channel Embedded CMPs Systems. In IEEE Transactions on Very Large Scale Integration (VLSI) Systems, (12769237):1351-1354, 30 June 2011. PDF [Comment]   Bibtex entry
Keywords: DRAM, Memory Performance, Multi-core Processor.  
<< InProceedings >> TOP
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Aarul Jain, Aviral Shrivastava and Chaitali Chakrabarti. LA-LRU: A Latency-Aware Replacement Policy for Variation Tolerant Caches. In Proceedings of the 24th International Conference on VLSI Design, Pages 298-303, IEEE Computer Society, 2011. PDF PPT [Comment]   Bibtex entry
Keywords: Cache, PTV.  
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Piotr Patronik, Krzysztof Berezowski, Stanislaw Piestrak, Janusz Biernat and Aviral Shrivastava. Fast and Energy-Efficient Constant-Coefficient FIR Filters Using Residue Number System. In Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2011. PDF [Comment]   Bibtex entry
Keywords: Power.  
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Yooseong Kim and Aviral Shrivastava. CuMAPz: A tool to Analyze Memory Access Patterns in CUDA. In Proceedings of the 48th Design Automation Conference (DAC), Pages 128-133, 2011. PDF PPT [Comment]   Bibtex entry
Keywords: CUDA, GPU, Memory Performance, Multi-core Processor.  
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Reiley Jeyapaul, Fei Hong, Aviral Shrivastava, Abhishek Risheekesan and Kyoungwoo Lee. UnSync: A Soft-Error Resilient Redundant Multicore Architecture. In Proceedings of the International Conference on Parallel Processing (ICPP), 2011. PDF PPT [Comment]   Bibtex entry
Keywords: Multi-core Processor, Soft Error.  
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Aviral Shrivastava, Jared Pager, Reiley Jeyapaul, Mahdi Hamzeh and Sarma Vrudhula. Enabling Multithreading on CGRAs. In Proceedings of the International Conference on Parallel Processing (ICPP), 2011. PDF PPT [Comment]   Bibtex entry
Keywords: CGRA, Coarse-Grained Reconfigurable Arrays.  
10 Add to my selection
Ke Bai, Aviral Shrivastava and Saleel Kudchadker. Stack Data Management for Limited Local Memory (LLM) Multi-core Processors. In Proceedings of the International Conference on Application Specific Systems, Architectures and Processors (ASAP), 2011. PDF PPT [Comment]   Bibtex entry
Keywords: Compiler Technique, Embedded Processor, IBM Cell, Memory Management, Scratchpad Memory, Software-managed multicores, Stack Data.  
11 Add to my selection
Ke Bai, Di Lu and Aviral Shrivastava. Vector class on limited local memory (LLM) multi-core processors. In Proceedings of the 14th international conference on Compilers,architectures and synthesis for embedded systems (CASES), Pages 215--224, ACM, New York, NY, USA, 2011. PDF PPT [Comment]   Bibtex entry
Keywords: Compiler Technique, Embedded Processor, IBM Cell, Memory Management, Multi-core Processor, Scratchpad Memory, Software-managed multicores.   Note: ISBN 978-1-4503-0713-0.
12 Add to my selection
Jing Lu, Yooseong Kim, Aviral Shrivastava and Chuan Huang. Branch Penalty Reduction on IBM Cell SPUs via Software Branch Hinting. In Proceedings of CODES+ISSS, Pages 355-364, 2011. PDF PPT [Comment]   Bibtex entry
Keywords: IBM Cell, Software Branch Hinting.  
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Reiley Jeyapaul and Aviral Shrivastava. Smart Cache Cleaning: Energy efficient vulnerability reduction in embedded processors. In Proceedings of the 14th international conference on Compilers, architectures and synthesis for embedded systems, Pages 105--114, ACM, 2011. PDF PPT [Comment]   Bibtex entry
Keywords: Cache, Cache Vulnerability, Soft Error.  
<< MastersThesis >> TOP
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Jared Pager. Improving CGRA Utilization by Enabling Multi-threading for Power-efficient Embedded Systems. Master's thesis, School of Computing, Informatics, and Decision Systems Engineering (CIDSE), 2011. PDF PPT [Comment]   Bibtex entry
Keywords: CGRA, Coarse-Grained Reconfigurable Arrays.  
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Last modified: Mon November 22 2010 16:16:55
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