nZDC Compiler

nZDC (near Zero silent Data Corruption) technique [1] is a compiler-level transformation based on assembly instruction duplication and result checking for soft error detection. nZDC transformation divides programmer available registers into two parts and duplicates program’s instructions. Immediately after each memory write operation the nZDC compiler inserts a load instructions from exactly same memory location as store and checks if the memory write operation has executed correctly.

LLVM 3.7 based compiler backend for nZDC transformation (compatible with ARM v8 ISA) can be downloaded from here.

For getting started on nZDC Compiler, and how to compiler and run programs, see README .

[1] Didehban, Moslem, and Aviral Shrivastava. “nZDC: A compiler technique for near Zero Silent Data Corruption.” Proceedings of the 53rd Annual Design Automation Conference. ACM, 2016.


LLVM-r Compiler

This is an under developed repository  which includes  LLVM backend for OpenRISC 1000 architecture with our implementation of several instruction duplication based error protection schemes (e.g. EDDI [1], SWIFT[2], SWIFT-R[3] and WholeSafe[4]). The implementation for error protection schemes can be found in this file.


[1] Oh, Nahmsuk, Philip P. Shirvani, and Edward J. McCluskey. “Error detection by duplicated instructions in super-scalar processors.” IEEE Transactions on Reliability 51.1 (2002): 63-75.

[2] Reis, George A., et al. “SWIFT: Software implemented fault tolerance.” Proceedings of the international symposium on Code generation and optimization. IEEE Computer Society, 2005.

[3] Reis, George A., Jonathan Chang, and David I. August. “Automatic instruction-level software-only recovery.” IEEE micro 27.1 (2007).

[4] WholeSafe: Instruction and Memory Triplication.


Error Detection by Redundant MultiThreading

This repository includes a python parser for EXPERT transformation [1] which utilizes natural core redundancy presented in modern multicore microprocessors for error detection. EXPERT transformation detects the manifestation of both soft and hard errors by creating a redundant thread for each program’s main thread and verifying the results of computations. The parser is developed for ARM v8-a ISA.

[1] So, Hwisoo, et al. “EXPERT: Effective and flexible error protection by redundant multithreading.” Design, Automation & Test in Europe Conference & Exhibition (DATE), 2018. IEEE, 2018.



gemV is an extension to the popular gem5 multicore simulation framework. gemV includes support for measuring the vulnerability against soft errors of the execution of a program on a processor architecture. Vulnerability is a  measure of the probability that a fault in a hardware-bit of the processor during the execution of a program will result in a failed execution. A fault in a processor may not result in a failure, because it may get masked. There are several masking effects in a processor, including microarchitectural masking, speculative masking, dynamically dead instruction masking etc.

The current version of the tool models the microarchitectural masking effect. A bit location b is not vulnerable at cycle c, if it will be overwritten next. The vulnerability of the program execution in the cycle c is the number of all the vulnerable bit in the processor, and the vulnerability of a program execution on a processor is the sum of a the vulnerability in each cycle.

The gemV Tool can be downloaded from here.

For getting started on gemV, and how to use the tool, see README .


For questions, comments, and feedback on the gemV toolset, please email us at :