Software Managed Reconfigurable Accelerator

SMRA: A Compiler-Simulator For Accelerated Heterogeneous Execution

SMRA (or Software Managed Reconfigurable Accelerator) is an initiative of the compiler-microarchitecture lab to boost and promote the development of reconfigurable accelerators. There are many compiler techniques or architectural explorations, researching on coarse-grained reconfigurable arrays (CGRAs). CGRAs are power-efficient accelerators that can accelerate non-parallel loops or loops with conditionals or loops with low trip counts and widely used to accelerate multimedia and embedded system applications. However, the CGRA research domain suffers from a lack of a common platform incorporating standard compiler and processor simulator environment, on which corresponding research can be developed or the results of novel solutions and gained acceleration can be validated.

Taking on the challenge, SMRA has been developed as an open-source and an automated framework in order to simulate the applications on coarse-grained reconfigurable arrays (CGRAs), which are associated with multi-cores. SMRA’s toolchain consists of LLVM based compiler to gem5 based processor simulator which aims to accelerate the c/c++ applications given as input. In this setup, CGRA is modeled as a core in the gem5 on which the performance-critical loops can be accelerated. Such an automated toolchain yields flexibility and boosts explorations at both compiler and microarchitectural level.

 

Software Release

SMRA’s toolchain can be downloaded from here.
More details about getting started with SMRA, please see ReadMe.
For any questions or feedback on SMRA development, please email us at cmlasu@gmail.com